IP to Go
Chip Estimate Fills the IP Gap

The race is on. Both competitors push pedals deliberately as the brakeless bikes start moving on the highly banked oval of the velodrome. Suddenly, before they have completed a second lap, the leader pulls his bike up the slope and comes almost to a stop, trying to lure his competitor into passing him on the inside. The duel that ensues is ironically typical of two-competitor sports like sprint cycling. Each cyclist strategically maneuvers his bike to try to gain the advantageous position – just behind the other in the aerodynamic wake. Sometimes, one of the cyclists will “track stand” his bike at a complete stop for what seems like an eternity (in reality, they can only hold still for a maximum of three minutes). Obviously, if there were more cyclists in the race, such a strategy would make no sense. The almost absurd approach is purely an artifact of the duopoly held by the two competitors.

For the two decades that FPGA design has existed, the methodologies have been following in the footsteps of ASIC design. As FPGA progress has accelerated and ASIC has stabilized, the gap has begun to close between the two design approaches so that it is often difficult to tell the difference between an FPGA and an ASIC design at many stages of the process. [more]

Accelerating RTL Analysis & Creation with Spreadsheets
by Michael Lee, Mentor Graphics Corporation

History of the Spreadsheet
In 1979, a young Harvard Business School graduate student envisioned a new methodology to effectively organize and process large amounts of data through variations of parameters to yield an exact what-if analysis of numerical models, utilizing something called a personal computer. The young graduate student, Dan Bricklin, created VisiCalc™, the first killer app for the nascent personal computer industry of the early 1980’s. Today millions of users depend on the progeny of VisiCalc, the most popular being Microsoft Excel™. Financial, scientific, and engineering fields have heavily leveraged the spreadsheet paradigm to organize, manage, analyze, model, and generate numerical and text data. Spreadsheets are now making their way into hardware design.

Mainstream Design Entry/Creation of RTL Designs
In two decades, ASIC/FPGA designs have increased in gate count by many orders of magnitude, and the methods of design entry/creation have moved from text to schematics/graphics and then moved back to text with the advent of hardware description languages (VHDL, Verilog, SystemVerilog, etc) nearly a decade ago. Each step in the evolution of the process of design entry/creation has been for reasons of managing ever larger designs and representing them in the most compact form possible for editing, comprehension, and synthesis into its end product: a logical netlist of gates. [more]