FROM
THE EDITOR
This week, Actel has conceived yet another way to create a useful, differentiated product offering from one of their two staple technologies - antifuse- and flash-based FPGAs. This time, they've tuned up ProASIC-3 (their flash FPGA family) for lower power consumption to create the new "Igloo" family. Our first feature takes a closer look.
Our second new feature is a contributed article from Ron Warner of Lattice Semiconductor explaining the use of parallel I/O at very high data rates in FPGAs. While the lion's share of recent interconnect attention has fallen on new gigabit serial protocols, Lattice believes that there are still a few gigabits left in simpler, parallel I/O as well.
Also this week, we are announcing a new upcoming Journal Webcast on coding techniques
for improved FPGA design, sponsored by Lattice Semiconductor. If you'd like to spruce up
your HDL for better synthesis results, head on over and  register.
Thanks for reading! If there's anything we can do to make our
publications more useful to you, please let us know at:
comments@fpgajournal.com.
Kevin Morris – Editor
FPGA and Structured ASIC Journal
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EVENTS & ANNOUNCEMENTS
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JOURNAL WEBCASTS
UPCOMING:
"Optimizing Verilog Coding for More Efficient FPGA Synthesis" sponsored by Lattice Semiconductor
Date: Tuesday, September 19, 2006
Time: 11 a.m. Pacific / 2 p.m. Eastern
Duration: 1 hour
Click to register
ON DEMAND:
"Designing 2Gbps Parallel I/O with the LatticeSC FPGA" sponsored by Lattice Semiconductor
 Click to view now
Lattice's new 90nm LatticeSC family -- General introduction, sponsored by Lattice Semiconductor.
 Click to view now
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Flash Freeze
Actel’s Igloo Attacks Power
Actel, the two-trick pony of programmable logic,
has just announced a new and novel platform that, once again, makes
maximum marketing advantage out of the peculiarities of
flash-based programmable platforms. The new FPGA family, dubbed
"Igloo," is perhaps the first FPGA with a solid chance
of carving a "must have" niche in the high-volume,
higher-competition, battery-powered world of smart phones and
similar mobile devices. To date, only CPLDs have penetrated the
rare-air BOMs of these cost- and power-sensitive embedded systems.
Actel's new Igloo FPGA family is based on their
popular flash-based ProASIC-3 line. In the world of FPGAs, flash
offers some compelling benefits when it comes to power
minimization. In developing Igloo, Actel has capitalized on those
advantages and added new power management features, targeting the
devices at extremely power-sensitive applications such as smart
phones. While you may have never seen "mobile phone" and
"FPGA" written on the same sheet of paper (unless there
was a prominent negative in between), Actel seems determined to put
FPGAs into these unlikeliest of sockets, attacking one of the last
and strongest bastions of ASIC domination. [more]
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Bit-Based Dynamic Alignment for Multi-Gigabit Parallel I/O
by Ron Warner, Lattice Semiconductor Corp.
The Role of High-Speed Parallel I/O
As I/O standards continue to evolve toward serialization, high-speed parallel I/O still plays an important role in specific chip-to-chip
applications in which either current serial technologies are cost prohibitive, or legacy demands it.
FPGAs are being used increasingly as
programmable SoCs, designed-in as an integral part
of the system data path supporting NPU, framer and
module- based source synchronous I/O standards such
as SPI 4.2, SFI 4.1, XGMII, HyperTransport and
Rapid IO. However, these applications require
devices capable of performing high-speed I/O
translation and processing. How can this level of
performance be achieved in an FPGA array? [more]
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