Electronic Elitism
DAC Divulges Design Tool Dilemmas

The 43rd annual Design Automation Conference (DAC) got underway yesterday in San Francisco, California. The technical sessions have begun, the exhibits are open, and the parties, PowerPoints and pejoratives have now commenced. Last night, at a media, analyst, and customer briefing dinner at the San Francisco Museum of Modern Art, Walden Rhines, Chairman and CEO, hosted a customer presentation explaining how Mentor's new Caliber nmDRC accelerates nanometer design rule checking by "hyperscaling" – a technique that takes efficient advantage of multiple processing elements to deliver many times the previous performance in giant DRC runs.

Beyond promoting the polygon-pushing power of parallel processing, Mentor's presentation also highlighted an interesting reality of today's Electronic Design Automation (EDA) industry – nanometer class design tools are getting bigger, faster, more sophisticated, more expensive, and consequently, more exclusive. Among the customers heaping praises on Caliber nmDRC for its parallelizing prowess were AMD and Intel – hardly the novice class in semiconductor design.

It is no secret that the number of ASIC and COT (customer-owned tooling) design starts has declined steadily over the past several years and is forecast to continue declining for the foreseeable future. Along with the decline in the number of design starts, the number of companies and designers engaged in ASIC/COT design has declined as well. At the same time, the cost and complexity of ASIC/COT design and the sophistication of the tools and methods required to complete a current-generation chip has risen almost exponentially.

For the companies that develop tools for these designers, this is both an opportunity and a curse. The opportunity side is obvious – designers need extremely sophisticated tools to complete their projects, and they're willing to pay top dollar to get them. For the company that can build the fastest, best-est, biggest super-deep submicron development and verification tools, the negotiation process is practically blank-check based. If you are in charge of a $15M-$30M SoC development project, how much would you pay for the software tools you need to help ensure that you will actually have working silicon at the end of your project? Well, I'll wager that you're not going to be choosing a weaker tool just to save a few thousand dollars. Spending a few extra thousand of the company's money to help insure your personal job security tends to be an easy decision.

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