a techfocus media publication :: July 18, 2006 :: volume XII, no. 03

FROM THE EDITOR

This week, we delve into the domain of digital design automation with the approach of the 43rd annual Design Automation Conference. This year, expect signs of a transition in the venerable industry, from fulfilling the requirements of yesterday's engineering problems to addressing the challenges posed by the new realities of semiconductor technology. The EDA industry, which has driven design to keep up with the staggering pace of semiconductor fabrication, is due for a makeover, and this year's DAC just might help show us the industry's new direction.

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Kevin Morris – Editor
FPGA and Structured ASIC Journal

LATEST NEWS

July 18, 2006

FSA Introduces Mixed-Signal/RF PDK Checklist Version 2.0; New Version Improves Design for Manufacturing by Correlating SPICE Models to Layout

Altera Announces First AQEC-Compliant FPGAs

July 17, 2006

CebaTech Announces Strategy to Deliver High-Value Internet Protocol Intellectual Property and Breakthrough ESL Technology; Company Leverages Ubiquity of C to Transform Software to Silicon and Break the IC Verification Bottleneck

ProDesign Adds Iridium Edition to CHIPit ASIC Prototyping Product Family

Liga Systems Unveils Breakthrough Hybrid Simulator That Boosts Traditional RTL Simulation by 10 to 100 Times

Xilinx Releases ISE WebPACK 8.2i - FPGA Industry's Only Free Fully Featured Design Suite

July 14, 2006

The Manitowoc Company, Inc. Statement Regarding Possible Offer for Enodis plc

July 13, 2006

PLDA And HARDI Electronics(R) Forge Strategic Partnership; PLDA's PCIe IP Controller Bundled with the HARDI ASIC Prototyping System

Atmel to Sell its Grenoble, France Subsidiary

July 12, 2006

ATEME Launches EASEE*: Audio/Video Software System for TI's DaVinci(TM) Technology; ATEME's EASEE Simplifies Development and Reduces Time to Market

Bluespec's SystemC Synthesis and Low-Power Technology on Display During 43rd DAC

Altera Customers Gain Performance, Power and Signal Integrity Advantages From Stratix II GX FPGAs

CURRENT FEATURE ARTICLES

DAC Previsited
Dawn of the Design Tool Decade
System-Level Sideshow
ESL Eases FPGA Design
Tooling up for 65nm
Xilinx Updates Software for Virtex-5
Logic Lockdown
Design Security Part 2
Security Blanket
Protecting Your System in an Age of Paranoia

Catapult Levels Up
Mentor Attacks ESL Subsystem Design

WEBCASTS

JOURNAL WEBCASTS ON DEMAND:

"Designing 2Gbps Parallel I/O with the LatticeSC FPGA" sponsored by Lattice Semiconductor
Click to view now

Lattice's new 90nm LatticeSC family -- General introduction, sponsored by Lattice Semiconductor.
Click to view now


DAC Previsited

Dawn of the Design Tool Decade

Exactly 299 days before "Cramming More Components onto Integrated Circuits" was published in Electronics Magazine, the first workshop of the SHARE Design Automation Project was held in Atlantic City, New Jersey. The SHARE workshop had papers with titles like "A method for the best geometric placement of units on a plane" and "Design automation effects on the organization." The magazine article began with the statement "The future of integrated electronics is the future of electronics itself."

With such generic paper titles and such an auspicious article intro, what has transpired since then that has inexorably linked those two seemingly obscure technical publication events? Pretty much everything.

15,071 days later (this coming Monday, in fact,) the 43rd annual Design Automation Conference (DAC) will kick-off in San Francisco, California.

The SHARE design automation workshop, held in Atlantic City in June 1964, is now counted as DAC #1. The Electronics Magazine article, published less than a year after that seminal if inauspicious design automation event, contained a small section that threw down the gauntlet to the fledgling design automation industry:

"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year ... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer."

In other words – "Hang onto your hats, design automation dudes! We integrated circuit folks may have managed to fabricate only a 100-bit shift register with 600 transistors so far, but by the time DAC #11 rolls around in 1975, there could be almost 65,000 transistors on a chip. We don't plan to be designing all 65,000 of them by hand, so we're gonna need a little help from those computer programs of yours. Beyond that, don't even think about what's going to happen by DAC #43 in 2006. We're talking billions!"

OK, maybe Gordon Moore's words were a little more reserved than mine, but I've had the advantage of over 40 years to think about what he wrote in that Electronics Magazine article, and… you know… I think he might have been onto something there. [more]

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