System-Level Sideshow
ESL Eases FPGA Design

The smartly dressed gentleman steps to the front of the makeshift stage alongside the hand-painted banner on his wagon. He looks down and lifts his pocket watch by its chain to check the time. He then surveys the gathering crowd, making eye contact with selected individuals as if he has a special message he is about to convey directly to them. He is a seasoned performer and a successful salesman. He will soon own this audience. "Laaaaaadies and gentlemen, gather around. Move up real close because I've got something veeeeery important to discuss with you." He deliberately lowers his voice as he nears the end of the sentence and drops his tone almost to a whisper, bringing the audience closer and stilling their conversation as they strain with anticipation to hear what will come next.

He pauses for exactly the right amount of time, then whips into his delivery with energy and zeal – "Have youuuuu been struggling to meet ever-tightening design schedules with more complex designs and a smaller, leaner design team?" He picks up the pace, enunciating each word with perfect clarity. " Do youuuuu find that the RTL methodology is too cummmmmbersome for today's more sophisticated FPGA designs? " He widens his eyes as he meets the gazes of each member of the audience, conveying an ominous fear. "Are youuuuuuu suffering the pain and ravages of MOORE's LAW?!?"

The crowd gasps.

"Welllllll, ladies and gentlemen, move in closer because I'm gonna tell you how to cut those design schedules. I'm gonna tell you how to Taaaaame that complexity. I'm gonna give you the secrets that will save you from the pain and agony and suffering of MOORE's LAW!" He leans down then softens his voice again "That's right, I'm talking about E – S – L. That's Electronic Sysssssstem Level design ladies and gentlemen. ESL will give you back the power. ESL will give you back the control. ESL will free you from the bonds of register-transfer level design and open up NEW LEVELS of ABSTRACTION for your design team!"

He points to an average-looking engineer, strategically planted in the middle of the crowd. "You, sir! Did you or did you not describe your Four Million Gate FPGA design using only TWELVE LINES of high-level code?"

The man replies sheepishly "Why yes, I did."

"Tell us, then, sir! Tell these good people how you cut your design schedules. Tell these good people how you freed yourself from the chains and bonds of register transfer level design. Explain to these fine folks how you used the methodology of the future – E, S, L – Electronic Sysssssstem Level Design… to elevate your design to a new level of abstraction and beat your competitors to market by months!"

If this sounds like a scene from a suite presentation at the upcoming Design Automation Conference – the Greatest Design Automation Conference on Earth, you're probably right. ESL is rapidly earning the title of "most over-hyped technology" in design automation history. With PowerPoint presentations that would make PT Barnum proud, EDA companies are pushing everything from transaction-level simulators to block-based design entry to high-level synthesis technology by slapping the "ESL" label on it and making outlandish claims about productivity improvements and time-to-market advantages. [more]