Catapult Levels Up
Mentor Attacks ESL Subsystem Design

In my book, ESL is a serious contender for the title of "worst technical term of the decade." As we've discussed before, the ESL label was possibly created by Dataquest in an attempt to create a category that could hold all of the EDA products that didn't fit cleanly into any of the previously established tool categories. As such, ESL turned into more of a "bucket" than a "category" as it snowballed down the mountain of misfit design software, accumulating technologies such as transaction-level simulation tools, graphical block-based design environments, high level language modeling, behavioral hardware synthesis, alternative hardware description languages, digital signal processing analysis and design tools, software/hardware co-development aids, and teaching English to non-native English speakers.

OK, maybe that last one wasn't Dataquest's fault.
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Complex ASIC Timing Verification Converges with FPGA-Based Designs
by Alessandro Fasan, Altera Corporation

Over the past few years, as FPGA devices have increased in density, speed, and started embedding dedicated memory, multiplier blocks, high performance intellectual property (IP), PLLs, and high-speed SERDES, they have become a viable alternative to implement complex designs and applications that traditionally targeted ASIC or ASSP-based designs . This trend however is stressing the limits of traditional FPGA static timing analysis tools and designer productivity is affected.

To meet market requirements and achieve target performance, FPGA design engineers are adopting new design styles and complex clocking schemes (i.e. clock multiplexing in 10M, 100M, 1G Ethernet applications), in addition to embedding in their designs source-synchronous clock interfaces (i.e. DDR and DDR2) that are difficult to analyze using traditional FPGA timing analysis. [more]