a techfocus media publication :: May 30, 2006 :: volume XI, no. 09

FROM THE EDITOR

This week, we line up our acronyms as our ECO feature is followed by a contributed COTS piece.  In our first new article, we take a look at Mentor's new engineering change order (ECO) capability that preserves placement between runs of synthesis and place-and-route for FPGA designs.  By preserving the placement of the part of our design that hasn't changed, we can lop off loads of headaches that we'd normally feel from iterating (or re-iterating) through the design flow to re-reach timing closure after a small change to our HDL.

Our second feature, contributed by Altera, looks at the commercial off-the-shelf (COTS) design strategy that allows military and aerospace applications to take advantage of leading-edge commercial technology, and how we can expand on the concept to further reduce costs and increase capability in demanding mil/aero applications.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Structured ASIC Journal

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LATEST NEWS

May 30, 2006

U.S. Air Force Director of Engineering for Materiel Command Delivers Keynote Address at The MathWorks Aerospace and Defense Conference 2006

Celoxica Unveils Next-Generation Video and Imaging Platform; RC340 Programmable Platform Fully Integrated Into ESL-design Flows for Real-Time Video, Image and Data Streaming Applications

Bluespec Plugs ESL Synthesis Hole in SystemC; Open ESL Synthesis Extensions to SystemC Create Unified Environment for Modeling, Design, Verification

Altera, IFI, SMSC Partnership Provides FPGA-Based, MOST Interface

May 25, 2006

Altera Enables ZAPiT Games' Breakthrough in Interactive, Console-Based Family Gaming

STMicroelectronics Certifies Mentor Graphics Catapult C Synthesis Libraries and Joins Silicon Vendor Partners Program

May 24, 2006

Arithmatica Announces Floating Point Library Customer in Advanced 3D Graphics Group

CURRENT FEATURE ARTICLES

Time for a Change
Mentor Modernizes the ECO
Going Beyond COTS Strengthens Mil/Aero PLD Applications
by Amr El-Ashmawi, Altera Corporation
Altera's Quartus II 6.0
Tools Turn up the Heat
Virtex-5 is Alive
The High End Gets Higher
On the Cutting-Edge of FPGA Design and Verification
by Allen Vexler, A2e Technologies
Altera Readies for 65nm
Fears Again Unfounded
Innovation Big and Small - Chapter 2
Bucking the Trend

WEBCASTS

JOURNAL WEBCASTS NOW ON DEMAND:

"Designing 2Gbps Parallel I/O with the LatticeSC FPGA" sponsored by Lattice Semiconductor
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Lattice's new 90nm LatticeSC family -- General introduction, sponsored by Lattice Semiconductor.
Click to view now

Time for a Change
Mentor Modernizes the ECO

Everyone knows the ECO. It is classic case of an acronym acting as a euphemism. Reducing a problematic situation to an established process represented by a simple trio of letters diverts attention from the underlying blunder. "Have Susan process Charlie's ECO before we bring up that final prototype" sounds much, much more palatable than "Thanks to Charlie's monumental screwup, Susan will have to attach a big red jumper wire that will now gleam like a beacon of stupidity from the back of the board on every one of our first million units."

As long as we have humans designing electronics, however, engineering change orders (ECOs) will be a reality of electrical engineering life. Few among us can say that we've participated in a project that has nailed everything right the first time. There is almost always a jumper wire, a software patch, or a new bitstream for that "glue logic" FPGA that we're now ever so happy we had the foresight to include on our board. FPGAs have often played the role of the modern-day jumper wire. If the bits came out in the wrong order, if the pinout was messed up on the ASIC, or if there was a timing problem on that input data stream that needed to be fixed, a strategically-placed FPGA could save the day. A few tweaks to the bitstream at the last minute, and a host of horrors could be hidden within the tiny walls of the FPGA's BGA pack. [more]

Going Beyond COTS Strengthens Mil/Aero PLD Applications
by Amr El-Ashmawi, Altera Corporation

The commercial off-the-shelf (COTS) electronics initiative of the mid-1990s occurred for two key reasons. First, acquiring customized components that could withstand harsh military environments came at a cost premium. Second, highly desirable leading-edge technologies, driven by larger market forces, were being developed for commercial applications. For these reasons, the U.S. government mandated that military contractors begin using a COTS approach, not only to reduce costs, but also to take advantage of emerging technologies.

COTS is based on the premise that military electronics programs could adopt or adapt commercially available components, boards, and systems, taking advantage of technological and economic benefits of commercial products. While COTS has been largely successful (the stories of $500 coffee pots and $5,000 toilets are long past), there is still clearly room to improve the way that commercial components meet the military's needs for reliable service in extremely demanding operational environments. Harsh environments typically require operational specifications supporting temperature ranges (from -55°C to +125°C), high altitude, high and low humidity, extreme vibration and shock, and potentially corrosive conditions. [more]

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