Altera's Quartus II 6.0
Tools Turn up the Heat

The FPGA market is a multi-faceted battlefield. Particularly between the largest two suppliers, everything is a race. There is a race to reach a new process node first, a race for the largest device, a race for the highest frequency, and a race for the lowest-cost parts. Silicon-based bragging rights aren't enough to keep the conflict interesting, however. Both Altera and Xilinx, the two market-dominant FPGA suppliers, invest huge amounts of resources in the development of tools and IP to complement their device offerings.

While not as visible as the war of the wafers, the contest to provide the most powerful, easiest-to-use, most broadly applicable tool suites at the lowest cost to their customers is a hard-fought battle. Recently, Altera announced their latest salvo in that conflict with the introduction of their newly-enhanced Quartus II 6.0 design tool suite for Altera FPGAs and CPLDs.

Altera's new Quartus 6.0 brings two headliner enhancements to the table that the company believes will benefit designers today in their 90nm designs, as well as in future designs at 65nm and below. The first is a new, ASIC-strength timing analyzer that the company has dubbed "TimeQuest." The second is a new project manager interface designed to improve team-based design of FPGAs. Both enhancements reflect the continued push of FPGAs into higher realms of design complexity and the corresponding need for more grown-up tools to support that design. Altera's decision to pursue these and other recent tool projects on their own rather than by partnering with third-party EDA companies also indicates a shift in strategy differentiation between Altera and their number one nemesis Xilinx.

Over the past several years, all but the most pedestrian FPGAs have reached a level of timing complexity that old FPGA tools simply cannot comprehend. Multiple clock domains, complicated timing requirements, and the migration of ASIC designs onto FPGAs for prototyping and early production have popped the buttons off traditional FPGA tools like Bruce Banner’s wardrobe in a fit of rage. In order to handle this timing complexity, third party EDA suppliers like Synplicity and Mentor Graphics bolted ASIC-style timing engines onto their synthesis tools several years ago. In addition to higher performance and capacity, these timing engines allow much more sophisticated and precise specification of timing constraints through their robust constraint languages.

One problem with third-party EDA-supplied FPGA synthesis tools supporting sophisticated timing is the inevitable impedance mismatch when coupling those tools to the FPGA vendors’ timing engines built into place-and-route. First, the EDA company tools use constraint languages like Synopsys Design Constraint (SDC) or Synplicity Design Constraint (um, also “SDC” – no relation) as the primary mechanism for the designer to specify the required timing relationships for their design. [more]