FROM
THE EDITOR
This week, Xilinx unveiled their new Virtex-5 family. With more logic, more speed, less power, and lower cost, V5 has everything one would expect in a new 65nm FPGA. There's more to the story than Moore's Law, however. Check out our latest feature article to find out.
Second, we have a contributed article from A2e technologies on their use of design tool capabilities in developing FPGA-based systems through their consultancy. Many features of leading-edge design tools go beyond "nice to have" by creating productivity advantages that can make the difference between failure and success in the business side of a consulting project.
Thanks for reading! If there's anything we can do to make our publications
more useful to you, please let us know at: comments@fpgajournal.com
Kevin Morris – Editor
FPGA and Structured ASIC Journal
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UPCOMING WEBCASTS
JOURNAL WEBCASTS NOW ON DEMAND:
"Designing 2Gbps Parallel I/O with the LatticeSC FPGA" sponsored by Lattice Semiconductor
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Lattice's new 90nm LatticeSC family -- General introduction, sponsored by Lattice Semiconductor.
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Virtex-5 is Alive
The High End Gets Higher
Innovation is a hot topic these days. We ourselves have billed innovation as "the fuel that powers technological progress" in our industry. You'd think, with the industry's first 65nm FPGA family rolling into production, we'd be saluting another salvo of innovation and inspiration from the world's largest FPGA company. We are, of course, but even more than that,
we're chronicling the execution of an equally important factor in high-tech success – learning. In their introduction of V5, Xilinx has shown us all that they're a company that learns – learns from their successes, learns
from their mistakes, and learns from their competitors. All this learning has manifested itself in the technology of Virtex-5, the marketing of Virtex-5, and the introduction of Virtex-5.
First, the expected. Virtex-5 is Xilinx's not-too-long awaited (it's here sooner than we expected) 65nm sequel to their current 90nm Virtex-4 flagship FPGA family. As Virtex-4 passes that flag to the next generation, we'll see the things one normally expects in such a transition. It turns out that Mr. Moore's string of over four decades
of precise prognostication is not over yet. Virtex-5 has more logic (a lot of it), more speed, uses less power, and will cost less than previous generations of FPGAs. How much better in all these critical areas? By the
numbers – 65%, 30%, 35%, and 45%. There. We're all done now, right? No complaints of burying the headline this time. We've spilled the beans in paragraph two and there's really no need to read on unless you want some insight beyond the marketing-driven myopia of press release perfection.
Still with us? That "[more]" link is coming up fast, so you'll have to make a decision. Do you want to know about the new underlying logic structure, the architectural changes for shorter, more predictable routing
delays, the additional family member, and what exactly the word "unveils" means this time? You'll have to bite the bullet and click to get the answers. Have we learned from the TV cliffhangers? Are we selling out to our own marketing department? Are our editors now being paid by the word?
[more]
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On the Cutting-Edge of FPGA Design and Verification
by Allen Vexler, A2e Technologies
As advanced FPGAs have grown to ASIC proportions in terms of size and complexity, their design and verification have become correspondingly more difficult. This has driven the need for greater expertise in the design and
verification of FPGAs. However, many companies, large and small, lack either the resources or the expertise for these demanding designs, so they turn to engineering service firms like A2e Technologies.
Typically projects reach us at a point in the design schedule where schedules are tight and time is of the essence. We need to get up to speed quickly on tough, challenging designs, and we must use cutting-edge technologies,
including simulators, that help us quickly understand the design and give us the flexibility to work with different languages in the same design environment. [more]
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