FROM
THE EDITOR
This week, Altera gave us a sneak peek at their 65nm development work for the upcoming Stratix III family. As expected, 65nm will bring us more logic, more performance, and lower cost from our FPGAs. For those of us that like to predict doom and gloom from problems like runaway leakage current and single-event upsets, however, it looks like we’ll have to take off our foil hats and wait another process generation or two.
Thanks for reading! If there's anything we can do to make our publications
more useful to you, please let us know at: comments@fpgajournal.com
Kevin Morris – Editor
FPGA and Structured ASIC Journal
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Altera Readies for 65nm
Fears Again Unfounded
We humans like to worry. Instead of being content with just living our happy lives, walking around enjoying the sunshine, eating our food, talking to each other on our mobile phones, and designing our next-generation electronic products, we mull and fuss about whatever nemesis might come along and end our little party. Will global warming overheat our junctions? Will earthquakes and volcanoes shake us into spilling our cocktails? Will comets and meteors crash into our spinning ball of fun, bringing on another ice age? With every additional year we speculate about new spoilers that might spell the end of our celebration.
IC technology is a bit like that too. With each passing process node, we predict the end of Mr. Moore's prediction. Will this be the last shrink? What will finally stop the steaming semiconductor locomotive's intrepid journey of exponential ecstasy? Will leakage current suck our power supplies dry? Will metal migration ruin our reliability? Will errant neutrons nail too many of our ground-level micro-transistors, sending us into single-event upsettedness? Every time the negative exponent on the dielectric dimensions grows larger, we strap on our sandwich boards and strut the streets shouting that the end is nigh.
FPGAs are on the point of that paranoic spear of semiconductor speculation. For the past several process generations, FPGAs have been the first complex devices to test the ropes on a new gate width, making them the prime subject of these prognosticators of process failure. As 90nm approached, we heard that leakage current would probably stop the show. FPGAs engaged in nothing more than holding onto their configurations would waste watts at such a frantic pace that practical use would be precluded by the countless coulombs coursing though their idle junctions. Nah. We were wrong.
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