a techfocus media publication :: March 28, 2006 :: volume X, no. 12


FROM THE EDITOR

Do you have a nice big blank BGA site on your board, just waiting for an FPGA? Is your boss giving you that "look" in the hallway? Did you fall for a marketing pitch and design in an FPGA device that isn't actually yet on the market? Did you forget to make a "Plan B?" It can happen to the best of us. This week, we dissect the demise of Craig, a semi-fictional designer, in order to learn from his mistakes.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Structured ASIC Journal

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LATEST NEWS

March 28, 2006

Bluespec ESL Synthesis Training Available Online; Video-Based Course Offered Free of Charge at Demos On Demand

The MathWorks Showcases Model-Based Design at SAE World Congress 2006; CEO to Participate in Panel; Experts and Engineering Students to Present on Using MathWorks Tools in the Automotive Industry

PLDA's Scalable x8 250 MHz PCI Express(R) IP Chosen by Tehuti Networks for 10 Gigabit Ethernet TCP/IP Accelerator

March 27, 2006

Altera Ships Stratix II GX FPGAs

Lattice Selects Rochester Electronics as Value Added Distributor

March 23, 2006

Spectrum Signal Processing Contracted by Harris Corporation to Support the U.S. Navy's Advanced Deployable System Program

March 22, 2006

Xilinx Virtex-4 FPGAs Provide Critical DSP Functionality in General Dynamics JTRS Radios

CURRENT FEATURE ARTICLES

Go, Stop, Yield
Dude! Where's my Chip?
Ask for Whom the Bell Tolls
RapidChip, or Structured ASIC?
Are You Designing with Too Many Significant Figures?
by George Harper, Bluespec, Inc.
What Do You Tell Them?
Explaining a Complex Career
Field Programmable Gate Arrays for Flexible and Fast Data Processing
by Michael Lundh, Fredrik Lundell, Said Zahrai, and Daniel Söderberg
Fusion Adds ARM
Actel's Embedded Wonder Gets Smarter
Image Processing Applications On New Generation FPGAs
by Rahul V. Shah, eInfochips Ltd.
SDR Prêt-à-Porter
ISR and Xilinx Roll Out Ready-to-Wear SDR

UPCOMING WEBCASTS

UPCOMING JOURNAL WEBCAST:

"Designing 2Gbps Parallel I/O with the LatticeSC FPGA" sponsored by Lattice Semiconductor
Join Journal Webcasts' Amelia Dalton as she once again hosts Lattice Semiconductor, this time to talk about how to beef up your I/O to achieve the most parallel performance possible in an FPGA today.

Click here to register!

NOW ON DEMAND:

Lattice's new 90nm LatticeSC family -- General introduction, sponsored by Lattice Semiconductor.

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Go, Stop, Yield
Dude! Where's my Chip?

Craig (not his real name) is the lead engineer on his company's most important project. So far, Craig has been worth his weight in gold (which is about $1.6M assuming $550 per troy ounce at his current weight of 2916 troy ounces). Besides working out regularly to keep those unwanted troy ounces off, Craig keeps up with the very latest FPGA technologies so he can make solid decisions in creating his company's new flagship electronic product.

This time, Craig chose a state-of-the-art 90nm FPGA as the centerpiece of his masterpiece. The product fit was perfect. Before this FPGA, there had never been a programmable logic product that could meet his price, density, and performance requirements. The selection of an FPGA, however, is what made the whole product concept work. His company could be among the first to introduce a board with support for the new standard, and they could rapidly upgrade the product in the field as the standard evolved. Furthermore, their customers would be able to upgrade to the next standard online by simply downloading a new bitstream to reconfigure the FPGA.

As soon as the next standard was stable, Craig's competitors would begin working to create a new line of boards. Craig's company, on the other hand, would be miles ahead with their products already in customers' hands and installed. It was a great market strategy enabled by a great design using the latest available programmable logic technology.
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