Ask for Whom the Bell Tolls
RapidChip, or Structured ASIC?

I was at DATE 2006, a tradeshow in Germany. My cell phone started buzzing with calls, voicemails and e-mail. People were stopping me on the show floor – pulling me aside, whispering rapidfire questions - always small variations on a theme. "Did you hear that LSI Logic is killing RapidChip? Do you think that structured ASIC is dead? Are other structured ASIC vendors pulling out as well? Will FPGAs wipe out the structured and platform ASIC space entirely? What's Altera doing? What about ChipX? Isn't AMI doing structured as well? Has eASIC been acquired yet? What have you heard from Fujitsu?"

Hey! I'm supposed to be asking the questions here.

The announcement had just hit the wire. LSI Logic was discontinuing (or de-emphasizing) the RapidChip family. The company would now focus its resources on the consumer and storage markets.

For a little background, LSI Logic's RapidChip family was one of the most successful and capable structured-ASIC offerings on the market. The company was obviously dead serious about the product line, having invested several years of intensive engineering and marketing effort in the project. The phrase "betting the company" had been bantered about in analyst and editorial circles. The common theory had been that LSI Logic had long been closely tied to the cell-based ASIC market, and that market was on a sustained decline. Structured and platform ASIC represented new hope – a market where rapid growth was forecast, rather than ASIC's long, painful demise in the face of increasing (and already staggering) development costs.
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Are You Designing with Too Many Significant Figures?
by George Harper, Bluespec, Inc.

Achieving timing closure in today's increasingly large and complex digital integrated circuit designs – irrespective of whether they are realized using FPGA, Structured ASIC, or even Standard Cell ASIC fabric – is becoming evermore problematic with the latest design targets running at aggressive clock speeds.

The majority of today's designers typically code in RTL using Verilog or VHDL. Also, there is some use of C/C++/SystemC coupled with behavioral synthesis technology in certain application areas. Unfortunately, both of these approaches have specific, but different, disadvantages associated with them. As we shall see, there is a new solution that uses an approach whose capabilities bridge these two domains.

Problems with Traditional RTL
When coding RTL in Verilog or VHDL, design engineers commence their portion of the development process by defining the micro-architecture of the design, including detailed control structures, bus structures, and primary data path elements. This micro-architecture also covers which operations are to be performed in parallel and which are to be executed sequentially, which portions of the design will be pipelined and the number of pipeline stages, and which resources (such as adders and multipliers) are to be shared between multiple operations.
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