SDR Prêt-à-Porter
ISR and Xilinx Roll Out Ready-to-Wear SDR

Just three weeks ago, Xilinx announced the latest version of their PlanAhead software, asserting among other things that they had simplified the daunting task of partial reconfiguration. We listened, and went so far as to include a section on this potentially ground breaking technology in our February 7 article on the subject (see article). We acknowledged our hesitation to get too excited about the idea, feeling that it would take a very brave soul indeed to jump in and give it a try. At the time, it felt like the equivalent of hanging your hat on academic fantasy. And even if it was real and it did work, you’d have to be some kind of Samurai black belt FPGA ninja to use it. However, after last week’s announcement on this same topic, including a full-blown real world application that takes advantage of this technology, perhaps we’ll need to apply the notion of partial reconfiguration to our own editorial archives.

Xilinx has partnered with Montreal, Canada-based ISR Technologies to deliver the industry’s first commercially available kit for a Joint Tactical Radio System (JTRS) software-defined radio (SDR) that uses two Xilinx technologies – embedded Virtex-4 FX FPGAs to leverage SoC capabilities, and partial reconfiguration using PlanAhead 8.1 software. Their numbers show that using this kit can result in a 2-3X reduction in both system power and cost. Speaking of power and cost, these are two of the biggest challenges facing the JTRS SDR industry. On the power side, a typical model for a four-channel JTRS SDR radio could use as many as 12 DSPs, not including memory or other types of devices. That means that signal processing alone could burn more than 70W. Although systems are often built in a modular fashion, that’s still a heck of a lot of power. Regarding cost, for the example system above you could be looking at a price tag in the thousands of dollars.

SDR is a killer app for unique capabilities that you can only find in an FPGA. In SDR, you have DSP algorithms that have to be accelerated into hardware to reach performance goals, and you have to be able to change those algorithms on the fly. The FPGA becomes almost a critical enabling technology for SDR. There may be other ways to meet the SDR challenge, but not as well as you can with an FPGA. [more]

Think You Know Where Structured ASICs Belong?
by Naveed Sherwani, Open-Silicon

 Over the past couple of years, the notion of Structured ASIC and Platform ASIC architectures, let's refer to both as Structured ASICs, have received a lot of attention from the chip industry. Structured ASIC proponents tout the concept as a way of getting near-ASIC performance and unit pricing without the high NREs and long and complex design cycles of ASICs. On the other side, skeptics dismiss Structured ASICs as a ploy to save what they consider to be a dying ASIC design industry. In reality, the benefits of Structured ASICs lies somewhere between these two viewpoints – exactly where depends from where you are looking.

The Trouble with ASICs
Yes, ASICs done with a traditional business model and methodology are expensive. NRE costs are projected to be $20M and up for chips designed at 90nm. They are also risky, with low cost- and design-time predictability along with relatively low reliability of first-time silicon success in the chip's target system. So, why do companies take on ASIC designs? They develop ASICs because they offer the lowest unit cost and highest performance of any silicon platform. The financial and design-time resources that cost so much means that the chip's design team can optimize the final chip for the most desirable tradeoff of chip area, speed and power. [more]