Upping the Low-Cost Ante
Lattice Raises the Stakes at 90nm

In the good old days, there was just one kind of FPGA – the "big" kind. Big is in quotes, of course, because even today's most modest, miserly devices are bigger and faster than the best we could muster a decade ago. However, as the high end of FPGA technology rode the rocket of Moore's Law toward the sky, becoming a viable solution for more and more complex applications, a new creature was born – the low-cost FPGA.

The concept seemed simple enough – "normal" high-end FPGAs were optimized for performance. Nothing was held back in getting the absolute best performance possible out of the flagships of the FPGA armada. Hard IP, the latest process technology, and copious quantities of die area were poured into never-mind-the-price programmable devices with the goal of getting the most LUTs we could manage flopping around at the fastest feasible Fmax.

Low-cost devices, however, were optimized for price instead of performance. Die area and manufacturing costs were king, and anything that could be spared was expunged from these (well-labeled by Xilinx) spartan devices. Prices plummeted, and low-cost FPGAs with respectable densities can now be had for the price of a good cup of coffee.

The problem with sustaining this dynamic duality, however, is competition. With no less than five programmable logic suppliers aggressively pursuing segments of the low-cost market, there is an almost irresistible temptation toward one-upsmanship. If your competitor offers one megabyte of block RAM, why not offer two? If your competitor's device doesn't include any hard-wired multipliers, why not add a few to yours? While you're at it, why not stay a couple steps ahead on the I/O capabilities of your low-cost line, just so you have an advantage? The easy answer to each of those, of course, is cost. Every incremental bell or whistle that you slip into your low-end devices raises your costs a little and hurts your competitiveness with the low-low-end of the market, particularly with those customers that don't plan to ring that extra bell. [more]

How to Avoid PCB Libraries Stifling FPGA Design
by Dave Brady, Mentor Graphics Corporation

• Reduced PCB signal trace length
• Reduced PCB signal layer count
• Reduced PCB component count
• Reduction in the size of the PCB
• Increased Quality of the PCB design

None of this is news. The FPGA vendors increased the flexibility of their device architectures years ago to create a vibrant array of I/O options at every signal pin on the device. All of the constituent elements appear to be aligning, enabling a new generation of complex system designs leveraging FPGA devices.

Early on, the EDA perspective revealed that one of the key barriers to concurrent FPGA/PCB design practice success was the historical "over the wall" hand-off between the FPGA and PCB design teams. In many corporate organizations, the FPGA and PCB design teams are not simply separated by "focus," the teams are quite often in different engineering organizations with different geographic locations. Challenging organizational barriers requires an intensive investment communicating the values gained by eliminating historical structures in search of operational excellence. Once again the FPGA/PCB integration solutions present a compelling value argument driving new behavior into execution based organizations. [more]