a techfocus media publication :: February 7, 2006 :: volume X, no. 05


FROM THE EDITOR

This week, Groundhog Day visits FPGA land as Xilinx announces version 8.1 of their PlanAhead floorplanning tool for FPGA design. PlanAhead is interesting and useful far beyond the traditional picture of floorplanners, however, as its visualization and analysis capabilities help with timing closure, team design, and even the dreaded but impressive partial reconfiguration trick. Our first new feature article takes a closer look.

Next, we hear from Steve Margerm at Cray about real world applications of reconfigurable computing using FPGAs. Some of today's most challenging problems are perfect candidates for acceleration using FPGA-based reconfigurable computing engines. Our second new article examines this practical side of the reconfigurable computing solution.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Structured ASIC Journal

LATEST NEWS

February 7, 2006

Altera and TelASIC Announce Breakthrough Power Efficiency for 3G/3.5G Wireless Base Station Radios

Xilinx Ships FPGA Industry's Only Compliant Programmable x8 PCI Express IP Core

Web Forums Now Active on Lattice Website

February 6, 2006

Aldec Releases Integrated Support for SystemC™ 2.1

First Silicon Solutions (FS2)(R) Introduces System Navigator(TM) for MIPS32(R) 34K(TM) Debug; FS2 System Navigator Supports PDtrace(TM) and Multi-VPE Debug

EVE to Exhibit Hardware-Assisted Verification Platform at DesignCon; Continuous Demonstrations of ZeBu Planned

National Semiconductor Introduces Industry's First Synchronous, Monolithic, 1.5A Buck Regulator With Inputs up to 36V

Altera's Stratix II FPGAs Enable 667-Mbps DDR2 SDRAM Data Rate

Xilinx Announces PlanAhead 8.1, Delivering a Two Speed-Grade Advantage Over Competing Solutions

February 1, 2006

OCP-IP Hosts 2nd Annual OCP-IP Pavilion at DATE; Conference Within a Conference Discusses Trends and Insight Surrounding IP Reuse

AMI Semiconductor Licenses Silicon Navigator Development Environment for OpenAccess; For Improved FPGA-to-ASIC Conversions

Bluespec Momentum Grows as Leading Mobile Semiconductor Firms Adopt Its ESL Synthesis; Applications Range from Baseband Processor to Controller and Chip Interconnect Designs

Opal-RT Technologies Inc. to Demonstrate the Latest in Real-Time Hybrid Powertrain Simulation at the SAE Hybrid Vehicle Technologies 2006 Symposium

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CURRENT FEATURE ARTICLES

Planning Ahead
Xilinx Updates Hierarchical Design Tool
Reconfigurable Computing in Real-World Applications
by Steve Margerm, Cray, Inc.
Status Quopia
Structured ASIC Captures Mindshare
Taming Embedded Multi-Core on FPGAs for Packet Processing
by Bryon Moyer, Teja Technologies, Inc.

This Engineer Walks Into a Bar…
Debunking the Nerd Myth
Erasing the Asterisk
Xilinx Boosts DSP Design with AccelChip
Beverly Hills 802.16
WiMAX, You da MAN

Field Programmable Journalism
Learning from a Programmable Publication


Planning Ahead
Xilinx Updates Hierarchical Design Tool

It's a cold February morning in a well-hidden corner of Silicon Valley. The air is perfectly still. The sun is just rising above the hills, although it isn't clearly visible through the dissipating ground fog cast over the region by the bay. There is a light frost on the grass, even though the temperature has been in the 40s all night. That's one of the big issues with fictional, metaphoric introductions to technical articles – continuity problems. These things clearly would never stand up to an engineering design review.

Any moment now, Silicon Valley Stan, the timing-closure groundhog, will emerge from his burrow. He'll whip out his smart-phone, maybe check the stock reports, listen to a couple of voicemails from his boss about the embedded software project falling behind schedule, start downloading his daily podcasts, and then step out of the threshold into the light. This, of course, is the moment of truth. If the angles and locations are just right, if the sun has penetrated the fog, if the route he follows on his way to work happens to follow just the right path – he may see his shadow. If he does, we'll have six more weeks of timing-closure problems, iterations through synthesis and place-and-route, changing RTL and constraints, moving I/O locations - all in a futile bid to foil the random hand of fate.
[more]

Reconfigurable Computing in Real-World Applications
by Steve Margerm, Cray, Inc.

Developers have long been intrigued by the potential of reconfigurable computing (RC) to accelerate some computationally-intensive high-performance computing (HPC) applications. But the barriers to achieving the order-of-magnitude performance gains RC can theoretically provide are well known: the complexity of programming for RC devices and the limitations of the hardware and software traditionally used to support them. As a result, software developers have focused on fine tuning applications to run faster on standard microprocessors, and have achieved important percentage gains.

Now, emerging systems like the Cray XD1 are bringing RC application acceleration into the real world and laying the groundwork to make order of magnitude performance gains a reality. At Cray, we wanted to see just how far we could push this technology.
[more]

EVENTS & ANNOUNCEMENTS

FPGA 2006, the ACM/SIGDA International Symposium on FPGAs February 22-24, 2006 in Monterey, CA presents the latest research in architecture, CAD tools, and device design. Novel uses of FPGAs will be discussed including cache emulation, customized soft-core processors, and specialized computation. A panel of leading experts asks, "Will Power Kill FPGAs?" Plan to attend this highly inspirational event!
To register, click here


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