Status Quopia
Structured ASIC Captures Mindshare

“You don’t understand,” my father patiently explained. “People have enormous collections of vinyl records. They’re never going to switch to a new format like compact disc, even if the sound and convenience are better. There’s just too much already invested.” Generally, Dad was a progressive, technically-savvy, keep-up-with-change kinda’ guy. On some issues, however, he just couldn’t see past the status-quo. His experience had built a level of technology-rooted myopia that his vision couldn’t overcome. When the new thing came along, even though its technical merits were compelling, he couldn’t imagine the cultural change that would cause it to catch on.

Structured ASIC has been that shiny, new technology on the block for a couple of years now. While everybody acknowledged that the approach had compelling technical and economic advantages, most people just couldn’t visualize its assimilation into mainstream system design. The more traditional approaches like FPGA, ASSP, Standard Cell, and fabless-COT had too much mental inertia. [more]

Taming Embedded Multi-Core on FPGAs for Packet Processing
by Bryon Moyer, Teja Technologies, Inc.

In public discussions about embedded multi-processing and FPGAs, most of the focus has been on DSP. But there’s another application area requiring embedded multi-processing that has remained elusive, not because of silicon deficiencies, but due to the lack of an easy methodology. That application is packet processing. Packet processing performance as high as 10 Gbps is possible in FPGAs, so the silicon is fast, but even single gigabit performance has required RTL and a hardware approach to design.

Many companies with projects involving packet processing work exclusively in software, predominantly C. They have infrastructures and methodologies based around software. They have hardware groups that provide them with the boards and systems they need, but see the bulk of their value in software. These companies do not want to learn RTL or use a hardware design approach; they want to work in C using a software approach. As a result, they have not included FPGAs in their consideration of packet processors. [more]