Introduction
Consumer electronics (CE) product developers are increasingly turning to programmable logic-based solutions to respond to the rapidly changing needs of consumers, and deliver new features and capabilities. This trend is caused by the recent proliferation of low-cost programmable logic offerings such as Altera® Cyclone™ series FPGAs and MAX®II CPLDs. This white paper describes how Pinnacle Systems, a leader in digital video solutions, leveraged programmable logic flexibility to address cost and board space reduction needs while delivering significant product differentiation in their Studio MovieBox Deluxe product . By using a programmable logic-based approach, Pinnacle Systems reduced their custom logic utilization and corresponding component cost by two-thirds, and integrated several ASSPs into a cost-effective consumer video appliance.

Custom Solutions for Differentiation
The common platforms used by CE product developers are ASSPs, ASICs, and programmable logic. ASSPs are not custom solutions, and provide no opportunity to differentiate, which is critical to sustaining the average selling price of the consumer product. Also, they generally implement standardized functions that are already commoditized in the market. Furthermore, ASSPs are not generally available for new, differentiated functions. The two remaining alternatives, ASICs and programmable logic, allow the CE product developer to differentiate the consumer product based on hardware modifications. Customizable Hardware Platforms for CE Products shows the relative advantages and disadvantages of ASICs and FPGAs. [MORE]

Field-programmable gate arrays (FPGAs) have a well-established position in every systems engineer’s toolbox. Taking advantage of their flexibility, engineers have used FPGAs for many years to rapidly prototype systems or in low-volume pre-production applications. When the communications- and network-driven Internet bubble took off at the turn of the millennium, demand skyrocketed for FPGAs in higher gate densities at any cost. Since then, however, FPGA requirements have changed dramatically. Today, as companies increasingly focus on the bottom line, engineers look for silicon solutions that offer both low unit and low total system cost.

While ASICs have traditionally offered the lowest unit cost of any silicon solution at high volumes, escalating time-to-market pressures, exponentially increasing NRE (non-recurring engineering) charges and the rising need to mitigate risk are preventing them from addressing system designers’ needs. Instead, a new ASIC alternative, the value FPGA, has emerged to address engineers’ requirements for a technology capable of meeting today’s shrinking development cycles with a low cost structure. This paper will define this new value-based FPGA market and will detail the various FPGA-based ASIC alternative solutions available. [MORE]

First introduced in 1998, Xilinx® Spartan™ FPGAs were the world’s first FPGA series for low-cost applications. With the introduction of the Spartan-3E family, Xilinx now has seven families of Spartan FPGAs in production – with more than 135 million units shipped to date. The Spartan series features the world’s most widely implemented low-cost FPGA architectures, designed into high-volume applications by thousands of engineers.

The Spartan-3 Generation Is composed of the Spartan-3, Spartan-3L, and Spartan-3E FPGA families. The Spartan-3 family (introduced in 2003) is optimized for I/O-centric designs, and is ideally suited for systems that have large I/O requirements. The Spartan-3E family is optimized for gate-centric designs, and is well-suited for designs that require a relatively higher gate-to-I/O ratio. The older Spartan-II/IIE and Spartan-XL families remain suitable candidates for legacy designs or for systems with higher core voltages.

Spartan-3 Generation FPGAs have found remarkable success replacing ASIC and gate array devices. For example, many flat-panel display systems employ Spartan-3 devices to manage the display driver and control functions. The ability to modify the design after layout and adapt the system to changing market conditions makes FPGAs highly desirable. [MORE]

Requirements for Bus Bridging, Interfacing and Control Bus bridging, interfacing and control are common functions in many electronic systems. The use of these functions spans virtually every end market segment, including automotive, consumer, communications, computing, industrial and military. In many cases, designers turn to programmable logic devices, either low-capacity FPGAs or high-capacity CPLDs, to implement these functions. However, neither class of programmable logic device has offered an optimal solution that fully addresses the requirements for devices implementing these functions, including:

• High pin-to-pin speeds to meet critical bus timings
• Instant-on to allow control logic to function ahead of other devices
• Upgradeability to allow for field upgrades
• High I/O to logic ratio to address multiple wide busses
• Flexible capabilities for data buffering
• Low power

Traditional CPLD and FPGA Approaches The CPLD architectural approach traditionally taken has been to build logic from Macrocells. Each Macrocell ORs together several wide (typically over 30 input) AND terms that are referred to as Product Terms. Historically, this approach has allowed fast wide logic to be implemented with a relatively simple set of design tools. [MORE]

Logic Navigator Overview
The ability to probe and analyze embedded signals in a design is important to rapid verification of large gate count and high performance FPGA designs. In a large design, entire logic subsystems may be essentially inaccessible from the pin IO, which limits the ability for direct verification. Proactive approaches to design debug can significantly improve the comprehensiveness and ease of analyzing complex FPGA designs.

Probably the most fundamental analysis requirement for FPGAs is to allow for trace and debug of groups of embedded signals and for analysis of signals in context of either other related signals or under specific triggering events. Several FPGA venders (Xiinx, Altera, Lattice) have developed their custom debug solutions for their FPGAs. Others, including Actel, Quicklogic, and Atmel have worked with First Silicon Solutions as a debug tools partner to provide debug capabilities to their customers. FS2 Logic Navigator is designed to provide this logic analyzer function for embedded FPGA signals. Since many of these tools have similar features, we use can Logic Navigator® as being of other logic analyzer features and operations as well.
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Abstract
This paper uses well-known routing estimation techniques to analyze the trends of routing area requirements for Coarse-grained Standard Metal Structured ASICs versus Field Programmable Gate Arrays (FPGAs) and Standard Cell. Standard Cell is typically a fine-grained cell architecture, with functions created out of standard single gate primitives, combined with custom metal interconnect, metal segments and vias fabricated with custom masks. FPGAs are standard products with programmable devices that are used to connect predefined metal segments together with coarsegrained programmable cells. By contrast Structured ASICs have regular arrays of coarse-grained programmable cells, and Standard Metal is a single custom via mask that interconnects the cells and preexisting metal segments together. The cell granularity, and the metal interconnect structure, of these diametrically different ASIC architectures, is analyzed and compared in this paper.

Routing Model
While there have been recent refinements to Rent’s rule based routing estimation [1][2], many routing area estimations are still based on Rent’s rule [3][4], a function, which estimates the number of pins on a block based on the number of cells in a block. Over 50 years ago, Rent pointed out that the number of pins P required for a block of logic that contained C cells could be estimated by P = K*CR where R is now called the Rent’s coefficient. This number is typically between 0.6 and 0.7 for random logic. For well-defined blocks, designed to minimize the number of pins on the boundary, this coefficient can be as small as 0.5. [MORE]