This white paper compares the performance of DSP applications in Altera FPGAs with popular DSP processors as well as competitive FPGA offerings. With higher performance, you can easily time-division-multiplex your DSP design to increase the number of processing channels, reducing the overall cost of your system. Table 1 shows the performance advantages Altera offers over other silicon solutions for DSP systems.

Figure 1 compares design performance in Altera Stratix II and Cyclone II devices to Xilinx Virtex-4 and Spartan-3 devices, respectively.

The Stratix II devices achieved an f MAX of over 350 MHz in 9 of the 17 designs, and two FIR designs exceeded 400 MHz. In comparison, only 2 of the 17 designs in Virtex-4 devices operated above 350 MHz.

The Cyclone II devices achieved an f MAX of over 200 MHz in 9 of the 17 designs, and one FIR design exceeded 300 MHz. None of the 17 designs in Spartan-3 devices operated above 200 MHz. [MORE]

Logic Navigator Overview
The ability to probe and analyze embedded signals in a design is important to rapid verification of large gate count and high performance FPGA designs. In a large design, entire logic subsystems may be essentially inaccessible from the pin IO, which limits the ability for direct verification. Proactive approaches to design debug can significantly improve the comprehensiveness and ease of analyzing complex FPGA designs.

Probably the most fundamental analysis requirement for FPGAs is to allow for trace and debug of groups of embedded signals and for analysis of signals in context of either other related signals or under specific triggering events. Several FPGA venders (Xiinx, Altera, Lattice) have developed their custom debug solutions for their FPGAs. Others, including Actel, Quicklogic, and Atmel have worked with First Silicon Solutions as a debug tools partner to provide debug capabilities to their customers. FS2 Logic Navigator is designed to provide this logic analyzer function for embedded FPGA signals. Since many of these tools have similar features, we use can Logic Navigator® as being of other logic analyzer features and operations as well. [MORE]

Multirate filters provide a practical approach to designing and implementing finite response (FIR) filters with narrow spectral constraints. By changing the input data rate at one or more intermediate points the filter lengths and computational rates can be greatly reduced when compared to a standard single-rate filter implementation. In this technique, the sampling frequency is first decreased and the actual FIR filter is implemented at the lower sampling frequency which considerably reduces the complexity of the filter.

Multirate filter designs can be easily modeled and analyzed using MATLAB and the Filter Design Toolbox. Once an acceptable response has been designed the behavioral model can be quickly converted into a synthesizable model and implemented on an FPGA using AccelChip™ DSP Synthesis and AccelWare™ IP Cores. This design flow marries the
efficiency and ease of use offered by MATLAB with the processing power of a DSP savvy FPGA such as a Xilinx Virtex 4 or an Altera Stratix II device.

Designing Multirate Filters Systems using Filter Design Toolbox
The Filter Design Toolbox provides an easy method to design and analyze behavioral multirate filters models. It includes functions for designing: Polyphase interpolators Polyphase decimators Polyphase sample-rate converters CIC multirate filters and multistage-multirate filters. [MORE]

Introduction
Orthogonal Frequency Division Multiplexing (OFDM) transceivers are widely used in wireless applications including ETSI DVB-T/H digital terrestrial television transmission and IEEE network standards such as 802.11 (“WiFi”), 802.16 (“WiMAX”), 802.20 (proposed PHY). Such transceivers have large arithmetic processing requirements which can become prohibitive if implemented in software on a DSP processor. However, the highly pipelined nature of much of the processing lends itself well to a hardware implementation. A flexible solution such as an FPGA implementation has the added advantage of allowing late modifications in response to “real world” performance evaluation, or for requirement changes if the initial design is based on a draft specification.

This paper describes an FPGA implementation of an OFDM transceiver design based on the core physical layer (PHY) requirements of the “WiMAX” 802.16-2004 OFDM specification. The use of IP cores for already well defined DSP functions can help to reduce the development time. Incorporation of multiple such DSP IP cores into both the design and the design flow is outlined. Various architectural design considerations are discussed, together with how features of the structure of the FPGA can be taken advantage of. Details are given of the final implemented design, the resulting performance and the total FPGA resources used. [MORE]

Overview

The high-performance EMIF bridge core reference design provides a connection between an Altera FPGA and the external memory interface (EMIF) of Texas Instruments (TI) TMS320C64x family of digital signal processors. The EMIF bridge core decodes external EMIF accesses and converts and forwards those accesses to the appropriate internal FPGA resource. Both digital signal processing (DSP) memory accesses and direct memory access (DMA) transfer operations are supported. The reference design is supplied with Verilog HDL.

Features

• Supports synchronous operation up to 133 MHz delivering new data every cycle
• Configurable as either EMIF A (32-bit or 64-bit data width) or EMIF B (16-bit width only)
• High-speed interface for developing FPGA co-processor systems

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