Leading the way in programmable innovation for more than 20 years, Xilinx adds to our rich history of breakthrough technologies with the sleek, powerful UltraController-II embedded processing engine. UltraController-II builds on the enormous adoption success of the first generation UltraController reference design released in January, 2004. This latest family member significantly optimizes system resources and enhances performance while providing new embedded capabilities to meet customer demands. All of this is delivered with zero risk, as the pre-configured and pre-verified microcontroller design is available free for the asking.

Based on the industry-standard PowerPC™ processor core immersed in the Virtex™-II Pro and Virtex-4 FX Platform FPGAs, a single UltraController-II reduces area by a stunning one-fifth over the original UltraController design. This ultra-compact design scales clock frequency to over 2X and raw performance to over 3X of the nearest competitor while power is reduced by over 4X compared to competing soft processor implementations. By leveraging both PowerPC cores in the Virtex family of devices, the dual UltraController-II also delivers two pre-configured designs while providing superior power reduction and resource optimization.

At the heart of the design is the 32-bit PowerPC 405 processor utilizing minimal FPGA resources by running code strictly from the integrated PowerPC 405 caches. This innovation eliminates the need for block RAM (BRAM) and has the complementary effect of reducing the controller’s power consumption. [more]

Memory Overview
Over the past several years the electronics market and, more specifically, the memory market has undergone significant change. Prior to the electronics industry downturn in 2000, electronic system designers were less concerned with the cost of the components going into their next design, and more concerned with the raw, maximum performance they could achieve.

Today, increasing competition and decreasing profit margins have forced system designers to reduce next generation product cost while maintaining, or even increasing, system performance. One industry segment that has experienced substantial growth as a result of this transition is DRAM memory, particularly Double Data Rate (DDR) SDRAM memory.

DDR Memory first came on the scene as a high performance, low-cost memory solution targeted primarily at the personal computer and other cost sensitive consumer markets. More recently, due to the economic pressures squeezing the entire electronics industry, non-consumer products have also begun to incorporate DDR memory. (Figure 1).

DDR is an evolutionary memory technology based on SDRAM. DDR SDRAM access is twice as fast as SDRAM, because DDR data transfers occur on both edges of the clock, compared to SDRAM, which transfers data only on the rising edge of a clock. [more]

Introduction
Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA software users, the same shrinking geometries that make their design problems tougher are also helping to improve the compute performance for their EDA tools.

But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches like simulation continue to lose ground. Why isn’t simulation speed keeping pace with device complexity? Because many new devices like 3G cell phones, internet routers, image processors, etc. require massive verification sequences that would take many CPU-years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software in order to fully verify a new SoC or system design.

Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a kind of chicken-egg problem: which comes first- the “final” hardware or the “final” software? [more]

Embedded designers seeking high performance processing inevitably face the cost/performance/power “Bermuda triangle” where the best of intentions can achieve any two of the key objectives, but fails to achieve all three. Custom ASIC designs are suitable for those few who can afford the time, expense, and risk involved, but as device geometries continue to shrink and ASIC design costs continue to grow, fewer and fewer applications can justify the expense of a fullcustom design.

FPGA-based embedded systems featuring multiple soft-core processors offer a powerful set of new options for the embedded designer. No longer are ASIC designers alone in their ability to configure performance-optimized systems-on-chip with custom tailored feature set. Now developers can change the performance characteristics of their embedded system right up to the time the product goes into final test. Developers also can extend product life cycle, getting to market quickly and upgrading both software and hardware features remotely over the Internet.

While the term “multi-processor” may conjure up memories of academic papers on “parallel processing,” commercial applications of multiple CPUs in a single device are much more straightforward. When starting a new design, developers must meet certain performance criteria. Partitioning duties among multiple soft processors not only provides the design flexibility to adapt to lastminute design changes caused by evolving standards or competing products, but also the ability to keep pace with this performance criteria. [more]

FPGAs have emerged as a critical component in many of today’s most demanding embedded system designs. Through a combination of unit costs dropping dramatically and the ease and flexibility they afford the designer, it is no surprise to see their adoption in embedded designs for products shipping into today’s hyper-competitive global markets. By establishing market presence, shaping customer preferences, attaining loyalty, building brand equity and of course achieving high profits, being first to market is critical to driving the success of most businesses. So how do you get your next great idea to market first, how do you control costs to make money once there and how do you protect your revenue stream and brand once your product is shipping in volume?

Getting to market first
Seeking excellence in all aspects of organization management, planning, development, manufacturing and marketing should help in achieving the ultimate goal of getting to market first, but from system design perspective, simplifying design through eliminating components is an important and all too often overlooked aspect of getting a design out the door. Many designers think that focusing on unit cost of FPGA-based solutions will give them the lowest total system cost and the quickest time to market, only to find that a vast array of complex and time consuming support infrastructure is required in their design to support their chosen device. In the low-cost (value-based) FPGA market there are several different technology choices available to the embedded system designer and the choice of FPGA technology makes a significant difference to the complexity of the embedded system design implementation and the overall time to design completion. [more]