More and Moore
Xilinx Looks Ahead to 65nm

Price, Performance, and Power – the three Ps of Moore’s Law -- have fueled four decades of technological fury. Each new process node brought us more gates per square meter of silicon, reducing price. Each shrink of the gate also brought us faster toggle rates, giving higher performance, and each narrowing also gave us the opportunity to operate at lower supply voltages, giving less dynamic power consumption. It seemed as if everything would improve exponentially forever.

Of course, nothing is free. There has always been another exponential curve at work as well – that of increasing costs. Each generation has cost geometrically more than the last, and the number of companies with the wherewithal to make the next node has withered with each wave. Smaller companies with fewer resources began to piggyback on the development efforts of larger companies, and a hierarchy of specialization emerged. Most systems companies long ago got out of the fabrication business and consolidated their efforts by going “fabless,” leveraging one of a few large fabrication facilities that quickly garnered much of the world’s semiconductor manufacturing business.

During the same period, many systems companies also relieved themselves of the burden of developing basic IC architectures, preferring instead to piggyback on a number of fabless semiconductor specialists (like ASIC and FPGA vendors) who created general-purpose architectures and tool flows to allow rapid development of systems from basic building blocks. Today, the accepted order of things is for systems companies to deal with fabless semiconductor companies (and sometimes EDA companies). Those companies then deal with the semiconductor fabs, EDA tool suppliers, and IP companies to put together the silicon platforms that they offer to their system-designing customers.

FPGA companies like Xilinx, Altera, Actel, Lattice, and QuickLogic have gained momentum over the past two decades by moving ahead in line at the semiconductor fabs. In the beginning, they were at the back of the pack, waiting for memory and ASIC companies to come up to speed on a new process node before they took their turn. Today, however, the leading FPGA vendors tend to be first, shaking out the each new process node before the rest of the industry comes along. [more]

Just What is Algorithmic Synthesis?
by Bryan Bowyer, Technical Marketing Engineer, Mentor Graphics Corporation

In a traditional FPGA design flow, crafting the hardware architecture and writing VHDL or Verilog for RTL synthesis requires considerable effort. The code must follow a synthesis standard, meet timing, implement the interface specification, and function correctly. Given enough time, a design team is capable of meeting all these constraints. However, time is one thing that is always in short supply. Deadlines imposed by time to market pressures often force designers to compromise, resulting in them to settle for ‘good enough’ by re-using blocks and IP that are over designed for their application.

In the past few years, tools and methodologies that support algorithmic synthesis have risen to help designers build and verify hardware more efficiently, giving them better control over optimization of their design architecture. The starting point of this flow is a subset of pure C++ that includes a bit-accurate class library. The code is analyzed, architecturally constrained, and scheduled to create synthesizable HDL.

For algorithmic intensive designs, this approach for creating verified RTL is an order of magnitude faster than manual methods. So if a designer is currently building and verifying 1,000 gates per day, the same designer using algorithmic synthesis can build and verify 10,000 gates per day. [more]