FROM
THE EDITOR
This week, we present FPGA Journal's version of "The Forbin Project" as we take our FPGA-sensitive shades inside Supercomputing 2005 in Seattle. Our special glasses can cut right through the plethora of parallel processors poised in stylish racks on the show floor, letting us see deep inside where FPGAs are being secretly wired in as accelerators for the toughest computing problems currently known to man. In a few years, when all those conventional processors start to melt away from excessive heat, the FPGAs may shoulder an increasingly important share of the bit-crunching burden.
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Kevin
Morris – Editor
FPGA and Structured ASIC Journal
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Saving Supercomputing with FPGAs
What We'll Do When We Hit the Wall
Massive racks of parallel processing Pentiums, Opterons, and Itaniums wasted watts at an unprecedented pace last week on the show floor at Supercomputing 2005 in Seattle. Teraflops, terabytes, and terrifying network bandwidths bombarded booth attendees looking for the last word in maximizing computational throughput. Convention center air conditioning worked overtime purging the byproducts of billions of bit manipulations per second as breaker boxes burst at the seams, straining to deliver adequate amperage to simultaneously power and cool what was probably the world’s largest temporary installation of high-performance computing equipment.
Meanwhile, the term “FPGA” was muttered in muted whispers in the aisles, hallways and conference rooms. It’s hard to believe that a cutting-edge, progressive, elitist field like supercomputing could itself have a lunatic fringe, but FPGA-based supercomputing seems to fall precisely into that precarious role – the fringe on the fringe. Picture shadowy, cloaked figures lurking in the lobby, pocket protectors securely in place under their overcoats, whispering to passers-by, “pssst – wanna see Smith-Waterman running at 50X speed on a $99 board?”
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