SerDes Sweet Spot
Altera Introduces Stratix-II GX

Sometimes, even the experts get fooled. Anybody who is intimately familiar with the FPGA industry would probably have predicted the same thing. With the epic Godzilla versus Mothra game of marketing and product one-upsmanship raging between rivals Xilinx and Altera for the past decade, the next move is often simple to anticipate. In the most recent rounds of action: Xilinx packs a hard punch introducing low-cost Spartan-3 as the first 90nm FPGA. Altera strikes back with Stratix-II as the first 90nm high-speed, high-density flagship offering. Each side then counters with the piece they’re missing, Altera with Cyclone II 90nm low-cost line, and Xilinx with Virtex 4, their 90nm flagship family. Now both sides assess their positions and prepare the next assault…

Since Xilinx’s V4 line also included high-speed SerDes (up to 10Gbps) Altera’s next play was obvious. Like chess masters zipping through a well-known opening, the moves are practically choreographed in advance. Altera just needed to roll out the “GX” extension to Stratix II indicating that they too had a 90nm SerDes capability. Given the industry’s propensity for superlatives, of course, Altera would probably be announcing something like rare-air 12Gbps SerDes so they could be “20% faster”… for a month or two at least, until...

Remarkably, Altera did the smart thing instead.

Not everybody needs a Formula-1 Ferrari to schlep their suits to the cleaners. In fact, the special design features that allow the car to travel at over 200MPH and handle over 1G lateral acceleration could actually make it a less-than-ideal vehicle for transporting laundry on city streets. There’s no good place to hang clothes, and the plastic bags would probably catch fire on the exhaust plenum. The same sort of thing is true for SerDes I/O. The design tradeoffs that allow transceivers to operate at 10Gbps can lead to sub-optimal signal integrity and higher power consumption at lower speeds.

Altera looked at today’s SerDes applications, picked the speed range most commonly used by their target markets, crazy-glued their egos to the desk, and designed the most efficient transceivers they could manage for the 622Mbps to 6.375Gbps range.

SerDes (Serialize/De-serialize) is a generic term that describes the function of transceivers that provide high-speed serial I/O functionality for a wide variety of standards and protocols. SerDes I/O has been rapidly displacing wide parallel busses in communications backplane applications, and is now moving into a wide variety of other applications where large amounts of data must be moved between physically separated devices. When adding SerDes capability to an FPGA, the FPGA vendor has to design special transceivers to support a diverse set of design goals over a huge speed range. This is a challenging engineering task involving numerous tradeoffs and compromises as well as a heavy dose of the dreaded analog domain. The proof in the pudding is the hole in your eye-diagram, and getting a big one over a wide range of conditions is difficult indeed.
[more]