Top-Flight Prototypes
Tips to Maximize ASIC Prototyping Results

It's a lifelong dream for many people to actually fly a plane on their own. The daring, carefree, wind-in-your hair pilot personality, however, is a bit of a myth. In real life, a good pilot is more like a good engineer. You plan and check everything meticulously. You want to find and fix any potential problems before you leave the ground, because once the wheels are up, it’s too late. Imagine you've been taking flying lessons now for several months, and you’ve finally logged the training hours, completed all of your exams, and qualified for your first solo cross-country flight. You arrive at the airport, brimming with excitement (and a bit of trepidation). The day is perfect, with crisp, cool air and clear blue skies. You've got a lot to do to prepare for this momentous occasion. You spent all night dreaming about the pre-flight planning, walking through every step a hundred times, making sure you didn't miss a beat. You're also ready with your pre-flight checklist to verify that your plane is safe to fly, and will perform to expectations when you're in the air.

When you get to the airport, there's a bit of a hitch. You're told that you’ll be performing your pre-flight inspection on a plane "very much like the one you're going to fly." "Oh," they say, "The engine will run slower than the one on your plane, and you'll see some other minor differences during the pre-flight, but it's OK." Then you learn that this testing should provide you with confidence that your plane is good to go. The word "yikes" comes to mind. That is, unless your day job is that of verification engineer who prototypes ASIC designs using FPGAs. Then, it's pretty much just another day at the office. [more]

How to Make An ASIC Prototype
by Lars-Eric Lundgren, HARDI Electronics AB

At HARDI Electronics, we started working seriously with ASIC prototyping in FPGAs about five years ago, and we quickly realized what the challenges were. First, it was obvious that the prototyping system needed to have the required capacity corresponding to the gate size of the ASIC. In year 2000, that was quite a problem since maximum FPGA capacity was a couple of hundred thousand ASIC gates and the ASICs were 10-100 times larger (1-10 million gates). Since then, the FPGA gate capacity has grown significantly. Today the largest available FPGA, the Xilinx Virtex-4 LX200, has an equivalent ASIC gate capacity at about 1.5 million gates. By putting a few FPGAs together, we can build a prototype for quite a large ASIC. On the other hand, ASICs haven’t stopped growing. A good rule is to say that FPGAs will continue to be about 1/10 the size of the average ASIC. Therefore, some designs will still need more than 10 FPGAs to make a good prototype.

However, the most critical parameter of an ASIC prototype in FPGAs is, in fact, not the gate capacity, but the number of interconnects between the different FPGAs. It doesn’t matter how many wires there are to connect the FPGAs together, it will still be too few. The reason for this is that inside the ASIC you normally have many wide busses going from one block to another. You’ll always need to use the biggest FPGA devices in the biggest packages. It doesn’t matter if the price is higher, always use the biggest package. [more]