Synplifying Physical Synthesis
Going Graph-based with Synplicity

When FPGAs flirted with the million-ASIC-gate density for the first time, a bell went off in many designers’ heads. This was not the tinny tintinnabulation of a bouncy little bicycle bell telling them, “Be alert, cyclist coming through.” No, this was the foul, foreboding clang of calamity to come. This was the thousand-ton tanker train of timing-closure nightmares turning around to bear down on them again from a new direction, threatening to bring back that all-too recent memory of indeterminate iteration in their ASIC design process to cause chaos in their new, happy, FPGA lives.

These ex-ASIC-aficionados went right back to the solution that had saved them before – physical synthesis. EDA companies worked feverishly to adapt algorithms from the ASIC world to the FPGA problem, frustrated at the lack of flexibility offered by FPGA architectures and the resulting shortage of solutions available. In ASIC, they could resize buffers, change routing, and move modules with fine-grained precision. With FPGA, they were gridlocked. Most of the fancy tricks just didn’t apply to the fixed architecture of pre-fab parts.

FPGA physical synthesis products relied on retiming, logic restructuring, re-doing placement, and replication to squeeze out the last few nanoseconds of negative slack from pesky critical paths. The lingering problems were the topology and the design flow. The topology of the FPGA was not so smooth and linear as ASIC. Small, fine-grained adjustments were not possible, and bigger ones sent waves of unpredictable alterations through the whole design, threatening to prevent convergence on a working solution. The FPGA design flow was never meant to accommodate physical synthesis, so building it into the process was like strapping a jetpack onto a street sweeper. [more]