Rationalizing Reconfigurability
The Importance of Being Programmable

About twenty years ago, there were two well-known approaches to custom IC implementation. The first, which we called “Full Custom,” was the high-end methodology. Polygons were painstakingly pushed across Calma screens by determined designers working to eek out every ounce of performance from fiery five-micron silicon technology. Full Custom design was difficult and expensive – not for the faint of heart or the financially challenged.

The second option at that time was Gate Array. Gate Array was for product teams with deadlines to meet and more important things to do than fighting with design rule violations and transistor-level layout problems. Gate Array offered lower risk, faster time-to-market, and reduced development cost. Economy of scale was on your side because only a relative handful of masks was required to complete the final personalization of a Gate Array, whereas Full Custom required a complete set, just for you.

Fast forward a decade, and a shift had occurred. Full Custom methodologies had almost dropped out of use except for mixed-signal or exotic-technology designs. Its place at the high end of the scale had been taken over by “Standard Cell” – a technology that brought some of the automated design techniques and module-level re-use of gate array to a more highly optimized environment. Standard Cell had inserted itself in between Gate Array and Full Custom and pushed Full Custom up and off the map.

At the same time, Gate Array’s position on the low end of the scale was under attack. “FPGA” had emerged, growing out of the much simpler PLD and PAL technology, and threatened Gate Array as the fast time-to-market method for getting custom functionality into silicon. Gradually, Gate Array gave way in the market to FPGA, relegated to a cost reduction option for successful FPGA designs going to higher volume.

For the next ten years, FPGA and Standard Cell ruled the roost. Each had slipped in below the prevailing technology and driven upward on the technology curve, uprooting the incumbent and stealing market share, starting from the base of the pyramid and moving upward. Standard Cell was for well-funded, high-volume projects that required maximum performance, minimal unit cost, or some combination of the two. FPGA was for lower-volume, fast turnaround designs that didn’t care as much about register-to-register delay as they did about design-to-cash-register delay. [more]