Mapping MAPLD
The Conference That Could

It’s difficult for a technical conference to get just the right balance. Too much tradeshow, not enough industry participation; too many irrelevant sessions, too many times over the same topic; not enough attendees, too many attendees… it’s like trying to hit your design constraints for power, cost, area, performance, and reliability all at the same time, while still meeting your schedule. You struggle to reach one goal only to find out that you’ve slipped behind on the others. It’s a fight to find a creative solution that will converge.

The eighth annual Military and Aerospace PLD conference (MAPLD) held last week in Washington DC seems to have found that elusive equilibrium, however. The 500-ish attendees create a comfortable-sized event - enough brilliant people so there’s always somebody very interesting to chat with, and not so many that you have to wait in line at the coffee bar. The size of the venue (the lower floor of the Ronald Reagan building on Pennsylvania Avenue) is about right to give you a workout as you sneaker-shuttle between the food, the technical sessions, and the show floor, but not so large that you have to catch a bullet train to make your next talk on time. The understated exhibit lounge provides a nice and useful supplement to the technical program instead of acting as a distraction. This is a worthwhile event for exhibitors, but not one where they feel compelled to build booths the size of Texas equipped with 50,000-watt sound systems and live white tigers jumping through flaming hoops with FPGA development boards clenched in their teeth.

The technical program here is definitely the star, and the schedule makes it easy to catch the presentations you’re interested in. Most of the time, there is a single track running in a large, comfortable auditorium. You can sit in one place and soak up the technology instead of spending half your time nervously studying your conference program, trying to apply ILP techniques to schedule your afternoon in real-time. The program is excellent, with an interesting blend of papers from industry and academia as well as fascinating and inspirational invited talks such as Dr. Steven Beckwith’s discussion of the startling scientific success of the Hubble Space Telescope. [more]

It’s Not All About the FPGA Anymore
by Bruce Riggins – Mentor Graphics Corporation

Introduction
FPGA logic design no longer rules the project schedule like it once did. Twenty years ago, implementing the logic in 20 and 24-pin programmable logic devices, such as 22V10s or PAL16R8s, was tricky, given the state of programmable logic tools at the time, but doing so certainly didn’t consume the lion’s share of the overall design effort. Back then, the deciding factor in project schedules was typically the design of the PCB onto which those devices were placed. As the sophistication of programmable devices has increased – evolving into the FPGAs commonly used today – the design-cycle ‘long pole’ has changed hands several times, with each change of ownership being dictated by a combination of device complexity and the overall state of EDA software available at the time to address various design challenges.

For the last eight or ten years, the design of FPGA logic has held the distinction of being the most intricate piece of the larger, board-level, project. As such, team leaders have usually deferred to the FPGA designers when it comes to setting schedules. However, that is beginning to change. Companies utilizing very large FPGAs, and even those using multiple, smaller devices, are starting to realize that the majority of the work is being borne by the PCB designer, who is tasked with meeting routing, timing, signal integrity, cost, manufacturability, reliability and a host of other constraints – all after being handed a database where the PCB itself has been given little, if any, up-front consideration. Device design complexity vs. board design complexity has come full circle and is settling somewhere in the middle. A recent EE Times survey suggests that while roughly 33% of companies have some mechanism to address the FPGA/PCB co-design issue today (usually with internally-developed tools and scripts), within two years that is expected to grow to 46%. [more]