Space Silicon
Racing Against Radiation Effects

Most of us know Moore’s law to have only one independent variable – time. Mr. Moore predicts that, as time goes by, the complexity of our electronic designs increases exponentially. One thing Mr. Moore never mentioned in public, however, is the secret second factor. Aerospace engineers have long been aware that Moore’s law has a little- known term in the denominator. This factor is something like “one plus altitude squared.” As your design gets farther from the ground, the fabrication technology goes back in time along the line of progress. Until recently, by the time you got your system into orbit, your design was effectively a couple decades behind on the technology curve.

However, over the past decade or so, FPGAs have changed all that. Now, you can create your space-bound design with near state-of-the-art semiconductor technology and still have a fighting chance of meeting the demanding requirements of electronics for space flight. As we discussed last year in our “FPGAs in Space” article, modern programmable logic devices offer an attractive alternative to high-NRE ASIC designs with space-proven processes. The typical ASIC NRE, amortized over the small production run of a typical satellite system, for example, dominates the cost equation. Zero-NRE programmable logic devices are far more economically attractive, regardless of their unit cost. [more]

FPGA Reliability in Space-Flight and Automotive Applications
by Martin Mason, Director, Flash Product Marketing, Actel Corporation and Ken O’Neill, Director, Military and Aerospace Product Marketing, Actel Corporation

High-reliability design considerations are fast becoming an art that system engineers have to undertake very early on in the design process, often beginning with a designer’s choice of system silicon. For designers seeking flexibility and time-to-market advantages, high-reliability FPGAs are a good choice. However, not all high-reliability designs are created equal. There is a broad spectrum of high-reliability designs out there today, from space-bound satellites to anti-lock braking systems in our ground-based vehicles. While there are obvious similarities between these two types of systems, there are also some key differences, all of which become important considerations when determining your silicon-of-choice for these applications. [more]

Migrating FPGA Virtual Gates to MROM Reduces Reliability Risk
by Kevin A. Kwiat, Ph.D., Senior Computer Engineer, Air Force Research Laboratory, AFRL/IFGA

Interest in FPGA reliability is not restricted to SEU environments. The US critical infrastructure, for example, often demands 24/7 operations and thus hi-reliability is frequently sought and very few, if any, of the infrastructure components are in SEU environments.

System failures are largely attributed to software-level errors such as unexpected input values, timing violations, and I/O shortfalls. To decrease the probability of system failure, many specialized, checking functions can be performed during runtime to make the software error-resilient. However, system performance suffers because the checking functions consume processor cycles that would otherwise be used for the mission software. In real-time situations this can create a designer’s dilemma: either forego a check so as to meet a deadline or run the risk of violating system safety if that check would have detected an error.  [more]