FROM
THE EDITOR
This week, we’re donning our green translucent visors, tightening our belts, whipping out our calculators, and cutting the fat from our bill of materials. Our newest feature looks at cost reduction techniques for those of us fortunate enough to get our designs into a production volume that makes high-end FPGAs impractical.
Our second new feature from LSI logic follows on last week’s article with a look behind the scenes in PCI Express. Greg Martin compares structured ASIC and FPGA implementations of the standard, and makes the case for a structured ASIC solution.
We’re very excited to be debuting our new Journal Jobs employment site this week ( www.journaljobs.com). We’ve upgraded our old job listings section to a full-blown technology employment site with search capability, automated resume submission, and a host of additional features. Registration is free, and it’s a great place to start your search for that next promotion.
We are also breaking all of our records with signups for our upcoming sister publication, Embedded Technology Journal ( www.embeddedtechjournal.com). It’ll be just like FPGA Journal, only for embedded design. Subscriptions are free, so stop by and register.
Thanks
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Kevin
Morris – Editor
FPGA and Programmable Logic Journal
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Dropping the BOM
Volume Up, Cost Down
We’ve happily harnessed the hurry-up, speed-racer, super-fast, time-to-market advantages of programmable logic. Our product got there first, and ran virtually unopposed in the critical, market-share-sweeping early days. We rule! Now, however, we are victims of our own success. Fast-following competitors have arrived on the scene with “me too” knock-off products, and it’s time for us to kick our game back into high gear. At the same time as we’re adding a few nice second-generation differentiators to our offering, we also have to reduce our costs to the absolute minimum. We want to have it all – more market share, better features, and the lowest price with the highest margin. It’s time to roll up our sleeves and whittle that bill of materials (BOM) back to the bare bones.
The Secret Sauce
Our first stop is our own design. We have to identify the essence of what makes our system special. We need to put it in a saucepan with some dry white wine and slowly simmer it down until everything boils away except for the really tasty, gooey part that sets our product apart from all others. Once this is identified, we’ll divide our efforts between building the most cost-effective implementation of our secret sauce and buying the best combination of standard functions to finish out the project.
Fighting NIH (Not Invented Here syndrome)
In the process of building any system for the first time, we accidentally re-invent a lot of wheels. This is normal and fine, but when it’s time to cost-reduce we have to be pragmatic. Even if we spent weeks designing what we think is the worlds coolest Ethernet MAC, our next-gen system probably won’t win or lose because of it, or because of our cool dual-port RAM controller, or because of any bread-and-butter function that’s available in standard IP. We’ll be identifying all of the non-differentiating components in our design and looking for the lowest-cost, lowest-risk, least-design-effort method of incorporating them into our new system. [more]
PCI Express Design Considerations
Platform ASIC vs. FPGA Design Efficiency
by Greg Martin, RapidChip Technical Marketing, LSI Logic
Implementing a high-speed PCI-Express core is a complex task, even for the most seasoned engineers. To further complicate matters, the choice of implementation technology can play a significant role in the final design characteristics. When evaluating FPGA and Platform ASIC technologies, there are a number of key considerations.
Smaller Footprint
A typical 8-lane (32Gbps aggregate) PCI Express interface can be implemented with a 64-bit data path running at 250MHz or with a 128-bit data path running at 125MHz. It is extremely difficult to successfully implement any reasonably complicated digital design (with ~20 logic levels) at 150MHz in an FPGA. Reaching anywhere near 250MHz for such designs is not possible, even with the latest 90nm FPGAs. Therefore an x8 PCI Express core implemented in an FPGA will require a 128-bit datapath clocked at 125MHz. By contrast, when implemented in a Platform ASIC, the same core can easily achieve 250MHz allowing the smaller, more efficient 64-bit datapath implementation to be used.
In a Platform ASIC implementation, all of the data paths will be half the width of an FPGA implementation. Since these data paths comprise a large portion of the entire design it will have a major impact on overall gate count. A typical FPGA implementation uses approximately 60% more logic resources than a Platform ASIC implementation. [more]
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