a techfocus media publication :: August 16, 2005 :: volume VIII, no. 07


FROM THE EDITOR

Does your design include a PCI interface? This week, in our new feature article “Express Yourself” Amy Malagamba shows you how to move your system into the express lane. Whether you’re using FPGAs, platform/structured ASICs, or full-blown ASIC/COT design, this article will give you the rundown on the standards, IP, tools, and technology you need to blaze past the gigabit barrier with PCI.

Also, if you’re designing embedded systems, be sure to subscribe early for our upcoming publication “Embedded Technology Journal” (www.embeddedtechjournal.com). ETJ will bring the feel, fun, and format of FPGA Journal to the embedded computing community with original articles, the latest news, and in-depth technical papers on the design and implementation of both hardware and software in embedded computing systems.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal


CURRENT FEATURE ARTICLES

Express Yourself
The Ins and Outs of PCI Express
Platform's Promise

Design Tools of the Future - Today
Algorithmic C Synthesis Fuels Functional Reuse
by Shawn McCloud, Mentor Graphics Corp.
Stretch Goals
Bridging the DSP/FPGA Gap
Optimizing Programmable Devices for Bus Interfaces, Bridges and Control
by Gordon Hands, Lattice Semiconductor Corporation
Crossing Over
Lattice Introduces MachXO
Considerations for High-Bandwidth TCP/IP PowerPC Applications
by Chris Borrelli, Xilinx, Inc.
Actel Adds Analog

There's Fusion in our Future
SRC Code
'Tis a Far, Far Better Compiler


Express Yourself
The Ins and Outs of PCI Express

“When I was your age, I walked 10 miles to school – each way – barefoot in the snow (OK, maybe not).”

“When I was your age, I had something called a record player, and I listened to albums, appreciating a band for more than the one song that got voted onto the top 20 on TRL.”

“When I was your age, I designed my systems using an ISA bus for my I/O interconnect. That’s how it was done. And we LIKED IT.”

It is the job of each new generation to move us forward, sometimes in small steps, sometimes in monstrous leaps. And so it goes for I/O interconnect. In the early 1990s, the first-generation Industry Standard Architecture (ISA) bus was slowly phased out in favor of the more robust Peripheral Component Interconnect (PCI) local bus architecture. PCI is a 64-bit bus, usually implemented as a 32-bit bus, running at clock speeds of 33MHz for a throughput rate of 133MB/sec. Next came PCI-X (meaning PCI-Extended). PCI-X didn’t stray far from PCI, maintaining the established parallel bus structure, but it delivered more performance, with a throughput rate up to 1 GB/sec.

High-speed peripherals like Gigabit Ethernet and USB began pushing the limits of the PCI parallel bus structure, demanding more and more bandwidth. Then along came PCI Express. Although it carries on the PCI name, it actually has very little resemblance to its forefathers. PCI Express has a layered architecture, with a software layer, a transaction layer, a data link layer, and a physical layer. It has abandoned the parallel bus structure for a two-way serial approach that carries data in packets along pairs of point-to-point lines. PCI Express bit rates are 2.5Gb/sec per lane direction, and is scalable up to 16 lanes (you do the math…).

But PCI Express isn’t a total rebel. It maintains backward compatibility with the older PCI bus structures, and core PCI attributes, including the usage model and software interfaces, are still in place. This means that existing applications and drivers are not changed. Essentially, it’s just the BMX-riding, iPod-listening, espresso-drinking, cellphone-carrying, X-Games watching member of the PCI clan – fast, smart, and a little bit complicated to understand at first. [more]


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