a techfocus media publication :: August 9, 2005 :: volume VIII, no. 06


FROM THE EDITOR

This week, our first article explores the new wave of design tools aimed at IP-based design. People have long been both promising and protesting the idea of rapid design by simple IP assembly, and a number of current and future products aim to use that approach to expand the market for FPGA- and structured ASIC-based embedded computing platforms.

Our second new feature, by Shawn McCloud, looks at the increased flexibility brought to IP re-use by C/C++ based algorithmic synthesis. By de-coupling the algorithm of your IP from any specific implementation architecture, you can increase re-use into a much wider variety of scenarios, even those that might have dramatically different performance, area, and power requirements.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal


LATEST NEWS

August 9, 2005

National Instruments Releases the LabVIEW Advanced Signal Processing Toolkit; New LabVIEW Toolkit Simplifies Time-Series Analysis, Time-Frequency Analysis and Wavelet Applications

National Semiconductor Boosts FPGA Signal Integrity

August 8, 2005

Axeon Hldgs UK Regulatory Announcement: Axeon Holdings Plc (“Axeon”): New Vindax Product for Easy Integration with MATLAB/Simulink

R. Associates Joins Nallatech's Growing Channel Partner Program; Companies are Using FPGAs to Reduce Costs and Increase Performance in Seismic Processing for Oil and Gas Exploration

August 8, 2005

Altera and TI Partner to Deliver Compliant, Low-Cost Programmable PCI Express Solution

Lattice Reduces Standby Current For Lattice XP FPGA Family by a factor of 1000

August 3, 2005

AccelChip Enhances Model-Based Design Tool Suite

Altera Ships Industry's Largest, Low-Cost FPGA


CURRENT FEATURE ARTICLES

Platform's Promise
Design Tools of the Future - Today
Algorithmic C Synthesis Fuels Functional Reuse
by Shawn McCloud, Mentor Graphics Corp.
Stretch Goals
Bridging the DSP/FPGA Gap
Optimizing Programmable Devices for Bus Interfaces, Bridges and Control
by Gordon Hands, Lattice Semiconductor Corporation
Crossing Over
Lattice Introduces MachXO
Considerations for High-Bandwidth TCP/IP PowerPC Applications
by Chris Borrelli, Xilinx, Inc.
Actel Adds Analog

There's Fusion in our Future
SRC Code
'Tis a Far, Far Better Compiler
A New Spin on FPGA Re-spins
by Juergen Jaeger, Mentor Graphics


Platform's Promise
Design Tools of the Future - Today

My kids were prodigious overachievers all the way through high school, and I’ve always been very proud of them. However, there’s a different kind of feeling you get if one of your children follows in your own footsteps, accomplishing something you also were motivated to achieve. I studied electrical engineering in college because I wanted to design computers. I had been fascinated by the potential of programmable systems from an early age, and I worked hard to hone my skills and to build expertise in the challenging discipline. In the course of my schooling, I learned that most computers follow the same basic architecture, and that the process of computer system design is usually a series of decisions about which particular components – processors, peripherals, memory, bus structure - best fit the requirements of your project.

Last week, my daughter finished the design of her first computer system. She selected a processor with enough performance, but kept the cost and power consumption in check. She struggled for awhile over bus speeds and RAM configuration, finally choosing a setup with more memory than she thought she needed operating at a frighteningly fast clock rate. She fiddled with a few power options before selecting a scheme that seemed adequate, then began choosing peripherals that were specific to her intended applications. Her O/S decision had already been made except for a few details, and most of the applications software that would be running on the system had already been designed in advance. [more]

Algorithmic C Synthesis Fuels Functional Reuse
by Shawn McCloud, Mentor Graphics Corp.

Reusable intellectual property (IP) has been touted for years as the best strategy for efficiently creating ever more complicated system on chip (SoC) designs. IP is certainly gaining traction in today’s advanced ASIC and FPGA designs. However, adoption rates fall far short of what industry pundits predicted just a few years ago. Remember those breathless scenarios of small design teams stitching together hundreds of IP blocks to create incredibly complex ICs in just a matter of weeks? The reality today is much more prosaic.

According to the July 2004 report from Semico Research, Semiconductor Intellectual Property: An Idea Whose Time Has Come, the overall IP market in 2004 was a little less than $1.5 billion. True, the market is growing, but $900 million of the market is dominated by generic CPU or DSP cores. While the CPU market has experienced compound annual growth rates of 27%, the remaining non-CPU IP market, called commodity IP, has experienced growth rates closer to 17%. The primary reason for the widening growth gap is the inability of commodity IP to stay differentiated given ever changing system requirements and silicon processes. The result is loss of value at a much faster pace when compared to CPU cores. [more]

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