Stretch Goals
Bridging the DSP/FPGA Gap

BUUUUUUZZZZZZ. That’s your alarm clock. Time to get up at 0-dark-hundred and head to the airport for that early bird flight to San Jose (or “insert your city here”). You’re so familiar with this trip that the flight attendants greet you by name. Your status with the airline is something north of Super Platinum Plus. While it’s nice to feel, er, “special,” wouldn’t it be cool if there was another way to get to where you’re going? Imagine that you could get in your car at 6:05 a.m. and drive to your destination city as fast as the plane could get you there. No security scan required (you long ago stopped wearing your favorite belt because it sets off the sensor), no long-term parking and shuttle bus from hell, no insufferably long line at the coffee counter, and we won’t even touch on the random draw of people who regale you with stories of their travels once you’re in your assigned seat. All of that would be gone, replaced by the comfort of your car, your favorite CD, your custom lumbar settings. Best of all, you wouldn’t need any special training to learn how to make your car drive like a plane. No pilot’s license, no flight training. You would be in control, surrounded by what feels familiar, but you would be armed with completely new capabilities – in this case speed (and perhaps a really good radar detector…).

At the center of our frequent flyer fantasy is a simple notion. Take something totally familiar (your car) and enable it with unheard-of capabilities. This idea forms the foundation of the innovative technology at Stretch, Inc., a company that does for the semiconductor world what that souped-up car did for your commute.

In embedded system design there is a constant struggle between having a flexible programmable solution that can vary with changing market dynamics, and delivering the cost/performance results required to create a differentiated product. ASICs and ASSPs really aren’t an option here. The market moves too quickly. General-purpose processors and DSPs offer flexibility, but often fall short on performance in compute-intensive applications. You could consider combining a processor with an FPGA, with the FPGA doing the tough stuff, but that increases your design complexity and adds cost. [more]

Optimizing Programmable Devices for Bus Interfaces, Bridges and Control
by Gordon Hands, Lattice Semiconductor Corporation

Requirements for Bus Bridging, Interfacing and Control
Bus bridging, interfacing and control are common functions in many electronic systems. The use of these functions spans virtually every end market segment, including automotive, consumer, communications, computing, industrial and military. In many cases, designers turn to programmable logic devices, either low-capacity FPGAs or high-capacity CPLDs, to implement these functions. However, neither class of programmable logic device has offered an optimal solution that fully addresses the requirements for devices implementing these functions, including:

•High pin-to-pin speeds to meet critical bus timings
•Instant-on to allow control logic to function ahead of other devices
•Upgradeability to allow for field upgrades
•High I/O to logic ratio to address multiple wide busses
•Flexible capabilities for data buffering
•Low power

Traditional CPLD and FPGA Approaches
The CPLD architectural approach traditionally taken has been to build logic from Macrocells. Each Macrocell ORs together several wide (typically over 30 input) AND terms that are referred to as Product Terms. Historically, this approach has allowed fast wide logic to be implemented with a relatively simple set of design tools. In addition, CPLDs typically have been implemented using non-volatile technology, enabling the logic to be available instantly on power-up, a feature known as “instant-on.” In contrast, the FPGA architectural approach constructs logic out of 4-input Look-Up Tables (LUTs). Figure 1 compares the two approaches. [more]