Crossing Over
Lattice Introduces MachXO

When I was a kid, my Dad had a big’ol vacuum-tube audio amplifier. It was massive, heated the room, and took several minutes to “warm up” before it was ready for duty. Sometimes the transformers would hum along with the music, which was OK if the tune was in a key that was a multiple of 60Hz. To me, the thing seemed a bit clunky compared with the transistor-based mainstays of the day. When I asked Dad about the amp, he’d always reply “Well, son, they used to make them all that way, but it got too expensive.”

Dad had a soft spot for the Dodo birds of technology. He was nostalgic for the era of aesthetic over-engineering and lamented the loss of beautiful but impractical designs of the past. He was much more knobs and meters than pushbuttons and digital readouts - a musician with a mechanical engineering degree for whom form did not always follow function. Together we watched the quiet demise of the points-and-condenser ignition, the 8-track tape, the rotary dial telephone, and many more.

Now we are all spectators at the dawn of the extinction of the CPLD. It’s a bit of a stretch to imagine that something as obscurely pedestrian as a programmable logic device could foster a fan following, but Lattice’s MachXO architecture announcement last week gave me that familiar feeling nonetheless. Unlike rival Altera with their Max II “CPLD” family, Lattice doesn’t pretend that their new MachXO device is a CPLD, even with a nod and a wink. While XO walks, talks, quacks, performs and prices like our familiar product-term friend, under the architectural hood lie the LUTs and interconnect of a non-volatile FPGA. [more]

Considerations for High-Bandwidth TCP/IP PowerPC Applications
by Chris Borrelli, Xilinx, Inc.

The TCP/IP protocol suite is the de facto worldwide standard for communications over the Internet and almost all intranets. Interconnecting embedded devices is becoming standard practice even in device classes that were previously stand-alone entities. By its very definition, an embedded architecture has constrained resources, which is often at odds with rising application requirements.

Achieving wire-speed TCP/IP performance continues to be a significant engineering challenge, even for high-powered Intel™ Pentium™-class PCs. In this article, we’ll discuss the per-byte and per-packet overheads limiting TCP/IP performance and present the techniques utilized to maximize TCP/IP over Gigabit Ethernet performance in embedded processor-based applications.

Overview
Gigabit Ethernet performance is achieved by leveraging a multi-port DDR SDRAM memory controller to allocate memory bandwidth between embedded PowerPC™ processor local bus (PLB) interfaces and two data ports. Each data port is attached to a direct memory access (DMA) controller, allowing hardware peripherals high-bandwidth access to memory. [more]