SRC Code
'Tis a Far, Far Better Compiler

“It was the best of times, it was the worst of times,
it was the age of hardware design,
it was the age of programming,
it was the epoch of synthesis,
it was the epoch of compilation,
it was the season of optimization,
it was the season of acceleration,
it was the spring of flexibility,
it was the winter of automation,
we had everything before us,
we had nothing before us,
we were all going direct to Hardware,
we were all going direct the other way--in short,
the period was so far like the present period,
that some of its noisiest authorities insisted on its being received, for good or for evil, in the superlative degree of comparison only.”
- Apologies to Charles Dickens

Our tale of two cities begins with researchers and engineers from two distinct camps with distinct goals attacking the same technical challenge from two different directions. On one side, electronic design automation (EDA) is working to raise the level of design abstraction for hardware engineers. High-level synthesis tools like Celoxica’s DK Design Suite and Mentor’s Catapult C flow forth from EDA, promising to revolutionize hardware design. Across the technological channel (the one that separates software and hardware engineering), high-performance reconfigurable computing companies like SRC are looking for a way to open up the awesome power of hardware acceleration to programmers needing new performance levels they can’t achieve with modern Von Neumann machines. The two camps meet at the FPGA. [more]

A New Spin on FPGA Re-spins
by Juergen Jaeger, Mentor Graphics

Back when FPGAs were simpler devices, in-system debug was sufficient. Turning a re-spin in response to a specification violation found on the bench was a quick and easy process. Life was great, since re-spins were essentially “free”. This is no longer the case today. One company recently spent three entire months trying to incorporate just one late-coming specification change, because the design team encountered difficulties meeting requirements after making that single change. This is not an isolated case; increasingly painful re-spins are no longer a rare occurrence. Clearly, this particular re-spin cost the customer dearly. So, what was different? The customer was designing a platform FPGA.

Platform FPGAs are pretty amazing products that offer excellent value to customers through increased capacity and many differentiating capabilities such as on-chip dedicated resources for storage, communications and DSP. Platform FPGAs present many new opportunities for using programmable logic that might not have been otherwise feasible. With these opportunities come new challenges. Essentially, when designing any platform FPGA, defect discovery must be consciously driven earlier in the design cycle, where the overall pain and cost for fixing errors is much less (figure). This can be accomplished by leveraging the increasingly convergent roles of synthesis and verification, and by adopting platform-specific design flows. [more]