Are These Guys Dense, or What?
Newest Class of FPGAs Makes Dense Cool

Context can drastically impact the meaning of a simple word. If you’re walking down the street minding your own business, you might find yourself feeling more than a little bit offended if someone calls you dense. You may even experience a brief but painful flashback to that dreaded walk through the gauntlet of cool kids lining the halls in school, hearing any number of rude, if inaccurate, comments (after all, who’s calling who dense?) thrown with casual abandon in your direction. Now, change the circumstance. You’re at a tradeshow, heading back to a demo station in your company’s booth. You find yourself facing another gauntlet of sorts, but this time it’s lined with people wanting to see your latest product and admiring its components, including, by the way, some “wicked dense FPGAs.” Suddenly, dense is cool.

This new class of FPGAs has just two members: Stratix II from Altera, and Virtex-4 from Xilinx. Although they both carry on their family names, following Stratix and Virtex-2 Pro, respectively, these 90nm device families deliver much more than standard generational improvements over their 130nm forefathers.

As expected, both device families offer higher density, lower cost per gate, and better performance. But before the vendors could dazzle us with all the trappings of their new offerings, they had to face the most daunting (and perhaps most anticipated) hurdle in making a move to 90nm: power. In an FPGA, power is broken down into two components: static and dynamic. It used to be that dynamic power (i.e., the power it takes to perform functions when the chip is running) was the big eater. But every time process geometry gets smaller, gates get thinner. Thinner gates leak more current (upping the static power consumption). There was a concern that if nothing was done to stop the trend, leakage current could all but take over as the power hog and potentially threaten the long-term viability of high-density FPGAs. [more]

FPGAs Enabling Consumer Electronics – A Growing Trend
by Suhel Dhanani, Sr. Manager, Xilinx

It was in the late 1990s that FPGA vendors first started exploring the low-cost, high-volume consumer market – a market that generally was ceded to standard, fixed-function devices. Exploring this market was made possible by the development of FPGAs with the right balance of features and the migration to advanced process nodes which helped to drastically reduce FPGA unit costs.

Historically for high-volume, price-sensitive applications, FPGAs were not the lowest-cost solution. However, as custom logic and FPGAs started to get pad-limited vs. core-limited, this started to change. Pad limitation occurs when the size of the die is determined solely by the number of required I/O pads and not by the amount of logic in the core. Many custom devices such as ASSPs and ASICs had been pad limited for some time. At process geometries below 0.5µ, FPGAs started to get pad limited for the first time. Price is ultimately dictated by die size - when devices get pad limited, the pricing differential between a custom and programmable product begins to narrow.

Today low-cost FPGAs are at the forefront of the process curve with architectures implemented on 90nm process technology. The relentless march down the process curve, coupled with increasing yields on larger wafer sizes (e.g. 12”), has resulted in a dramatic decrease in FPGA costs. For example, the cost per 1000 logic cells for Xilinx 90nm Spartan Series FPGAs has fallen by a factor of 30 since 1998. [more]