Lattice Launches XP
Non-Volatility at the Forefront of FPGA

There’s something of a Renaissance going on at Lattice semiconductor right now. Since forming their partnership with Fujitsu about a year ago, the company has sustained a steady stream of relevant announcements of new, competitive product lines. Not content to stay put in the commodity CPLD business, Lattice is mounting an aggressive campaign to capture a share of the emerging value-based FPGA market.

This week, Lattice stepped up their attack with the announcement of their new Lattice-XP line. Continuing the recent “Wolf in Sheep’s Clothing” trend in flash-based programmable logic, this family is a hybrid technology, seeking the benefits of non-volatile flash technology combined with the usual advantages of SRAM-based FPGAs. Lattice accomplishes this blend by adding on-chip flash RAM, which is capable of configuring the SRAM-based LUT architecture (the same as in their new EC and ECP lines). This makes Lattice-XP a single-chip, non-volatile FPGA with all the benefits and performance of an SRAM-based technology.

While Lattice’s EC and ECP lines seem poised to directly compete with Xilinx’s Spartan-3 and Altera’s Cyclone II, XP aims more at Actel’s recently announced ProASIC 3 line. With four aggressive companies investing heavily in the low-cost, high-volume, value-based FPGA market, the winner will definitely be the consumer. Lattice’s announcement heats up the competition and states once again that the rules and conventions of the previous FPGA market do not apply in this new space. For years, FPGA companies have competed along the same basic battle lines, derived from the needs of the telecom and networking industries. Raw performance, capacity, and reprogrammability were at a premium. Cost, power, and security were back-seat concerns. [more]

High-Density FPGA-to-ASIC Conversions using Structured ASIC: Fills the Gap
by Rick Mosher and Bob Kirk,
AMI Semiconductor, Inc.

Introduction
Managing the increasing complexity of today's digital applications calls for new design strategies. Risk, cost and time-to-market (TTM) can make or break a product development. While many designers are turning to FPGAs to reduce risk and improve TTM, the staggering per unit cost of high-density FPGAs quickly becomes intolerable for even low volume applications. Cell-based ASIC solutions offer much lower per unit cost, but the NREs for deep sub-micron technologies are becoming cost prohibitive. Structured ASICs fill the gap by offering excellent per unit cost and reasonable NREs. This paper describes a design flow starting with FPGA prototyping followed by conversion to a structured ASIC. The paper then describes how structured ASICs can be used to support a range of applications and how they can be used to quickly introduce cost effective, complex, digital products to market with minimal risk.

1. Comparing The Different Hardware Platforms
When selecting a hardware platform, the designer has many different options for complex digital designs including field programmable gate array (FPGA), cell-based application specific integrated circuit (ASIC), application specific standard product (ASSP) and structured ASIC technology. [more]