Simulator Savvy
Getting the Most From Your HDL

Most of us picked up HDL design the way we discover a new city. We land at the airport, and a taxicab drops us off at some arbitrary location - a hotel perhaps. From that point, we branch out in an ad-hoc manner, discovering things mostly by accident, and gradually building a mental picture of the place for ourselves. Different people may develop entirely differing views of a place depending on when and how they landed there and how their luck went in this semi-random discovery process. Much of what you discover first is based on what you were trying to accomplish when you arrived – attending a conference, visiting relatives, or maybe hitting the tourist attractions.

In HDL-based electronic design, this ad-hoc learning process can lead to dramatic differences in the style and efficiency of the HDL we create. Because both the verification and implementation tools are automated, we also get dramatically different results. These differences often determine the success or failure of our project. We may be efficient and lucky and end up with a design that verifies smoothly and implements correctly the first time, or we may find ourselves in a quagmire of debugging, modifying and completely re-writing with a design that won't synthesize cleanly, gives unsatisfactory results, or isn't even suited to efficient debug and analysis.

There are, however, a number of things you can do to give yourself the best chance of success. After consulting with a number of experts, here is our list of recommendations and best practices for getting your HDL-based design off on the right foot. [more]

The Impact of Timing Exceptions on FPGA Performance
by James Henson, Product Engineer, FishTail Design Automation Inc.

FPGA designers are typically working with prototype designs without much synthesis history, so on the first pass of the design they will not have developed a set of false path and multi-cycle path constraints. FishTail’s Focus tool can generate false path and multi-cycle path timing exceptions for the FPGA designer before the first synthesis run. These timing exceptions have the ability to improve FPGA QoR by relaxing constraints on the timing paths of the design and potentially allow the FPGA to run faster. In this paper we have studied the impact of timing exceptions on nine designs using Synplify_pro from Synplicity for logic synthesis, Xilinx tools for place and route, and Focus from FishTail to generate false and multi-cycle path timing exceptions. We compare the design’s maximum clock frequency before and after place and route, with and without timing exceptions. In about one quarter of these designs, the timing exceptions can make a one-speed grade improvement in FPGA performance after place and route.

FishTail’s Focus is designed to identify the timing exceptions in the design, and requires data that is normally already available for your design; synthesizable RTL, clock definitions and boundary constraints. Focus generates false and multi-cycle paths in industry standard constraint formats. Focus also provides the ability to verify the generated timing exceptions through assertions that can be checked as part of functional simulation. [more]