Flash News Flash
Actel Unveils ProASIC3

Could this be the iPod of FPGA families? Has Actel created the happy little "chip that could" to take on the SRAM-dominated titans of the low-cost FPGA battlefield? Will ProASIC3 Development boards be proudly displayed on the desks of any development team that wants the nice, clean look and feel of a secure, single-chip, ready-at-power-up, low-power, no-hassle solution to their high-volume, middle-of-the-technological-road design problem?

Like other programmable logic vendors, Actel has noticed that cell-based ASICs are becoming an increasingly specialized solution for high-volume electronics products. Only the best-funded, most risk-immune, highest-volume-and-performance applications can realistically justify the creation of a cell-based ASIC solution for a new product development effort. There is a growing mainstream of systems companies that are turning to FPGA and structured-ASIC solutions, even at very high production volumes. The enormity of this opportunity has brought Xilinx, Altera, Lattice, and now Actel into fierce competition for this emerging market. [more]

Structured ASIC Starting Line
Vendors Announce New Families

If the value of structured ASIC as a gap-filler between programmable logic and cell-based ASIC is still in question, there are at least two companies on opposite sides of that gap where a decision has clearly been made. Both LSI Logic and Altera unveiled new families this week aimed at attacking this new and potentially lucrative segment of the silicon landscape. Interestingly, both companies' involvement in structured ASIC can be viewed as a defensive move. As a leading supplier of cell-based ASICs, LSI shored up its defenses against attack from the other side of the FPGA/ASIC border a couple of years ago by creating its RapidChip structured ASIC family. The low-risk, low-NRE, high-performance solution provided a welcome alternative for design teams that were possibly about to fall off of LSI's radar due to skyrocketing NREs for cell-based ASICs.

On the Altera side, structured ASIC poses a threat to the high end of the FPGA price/performance curve with a more potent product that mitigates the ASIC NRE penalty. With their introduction of HardCopy structured ASICs, they employed the "join them" strategy by offering up their own structured ASIC solution, with the kicker of a smooth migration from FPGA-based prototyping and early production, straight into structured ASIC cost-reduction. [more]

Considering the Total Cost of FPGAs
by Martin Mason, Actel Corporation

Field-programmable gate arrays (FPGAs) have a well-established position in every systems engineer's toolbox. Taking advantage of their flexibility, engineers have used FPGAs for many years to rapidly prototype systems or in low-volume pre-production applications. When the communications- and network-driven Internet bubble took off at the turn of the millennium, demand skyrocketed for FPGAs in higher gate densities at any cost. Since then, however, FPGA requirements have changed dramatically. Today, as companies increasingly focus on the bottom line, engineers look for silicon solutions that offer both low unit and low total system cost. While ASICs have traditionally offered the lowest unit cost of any silicon solution at high volumes, escalating time-to-market pressures, exponentially increasing NRE charges and the rising need to mitigate risk are driving up ASIC unit costs, preventing them from addressing system designers' needs. [more]