Debug Dilemma
Simulate or Emulate?

What goes in software, and what goes in hardware? In most complex digital designs, the answer to this key question will determine success or failure of the architecture of the system. Put the wrong piece in software and performance suffers from overloading the processor. Put the wrong piece in hardware and your cost rises from the additional gates, static power consumption goes up, and flexibility and maintainability of the system drop significantly.

It turns out that the software versus hardware battle is going on in parallel in your design environment as well. With modern FPGA development boards, embedded logic analyzers and debuggers, and purpose-built emulation systems, hardware in the loop (HIL) debugging and verification has rocketed to prominence. HIL is not the panacea of programmable logic debug, however. As our friends in ASIC design can tell us, software simulation, formal verification, and yes, HIL emulation all have a significant contribution to make to our design process. As in system architecture, the key decision is what part of your design and verification should be conducted in software versus hardware.

Debug and verification account for the lion's share of time and effort in any significant digital system project, whether targeted to FPGA, structured ASIC, or cell-based ASIC technology. For ASIC design teams, verification is a life-or-death proposition where the success or failure of the project depends on getting the design right the first (or more likely second) time. For FPGA-in-production teams, the penalty of verification failure is much lower, but there still is a sinister swamp of stagnation awaiting those who go too quickly into hardware and never emerge from the quagmire of interrelated bugs. [more]

Deliver Products On-Time with RTL Hardware Debug
by Dennis McCarty, Technical Marketing Manager, Synplicity

Crunch time on projects always seems to come during lab debug. That's when the FPGA, software and PCB all come together for the first time. It's also the last, and frequently, most difficult phase in the project. Any slack time in the schedule has long since been eaten up by unanticipated delays of one sort or another. The entire team has to work together on the same thing and in the same place, possibly for the first time.

Many developers put off thinking seriously about the latter stages of the project and what tools they might need once they get there. There's so much to do initially in specifying the design, partitioning it and keeping all the parallel efforts on track and in sync to consider what you’ll do when you get to the lab.

But when you're budgeting the project, it's important to consider what tools you will need on the back end as well as the front to ensure success. Simulation is fine for logic verification in a test bench environment. But verification in an actual system running at speed is another matter. Most projects require hardware verification in the lab with the system software operating on an embedded processor and interacting with other logic on the FPGA. You use hardware verification tools to debug that system. [more]