| FROM
THE EDITOR
This week we begin a two-part
series of articles focusing on progress in FPGA technology for
digital signal processing (DSP) applications. First, we put the
spotlight on the design tools and methodologies required to get
from common DSP algorithm development environments such as The
Mathworks’ Matlab into a hardware implementation
in your favorite FPGA technology. There has been significant progress
in this methodology since we summarized it over a year ago, and
we’re excited to offer this new overview.
In a couple of weeks, we’ll also be
taking a look at the hardware side of the DSP dilemma. FPGA vendors
have been hard at work creating new, more capable DSP-specific
hardware and deploying it on ever-more-thrifty FPGA platforms
creating a truly unprecedented price/performance ratio for custom,
high-performance processing.
Thanks
for reading! If
there's anything we can do to make our publications more useful
to you, please let us know at: comments@fpgajournal.com
Kevin Morris – Editor
FPGA and Programmable Logic Journal
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Destination DSP
Methodologies for Signal Processing Success
As FPGAs have earned greater acceptance as the platform of choice for
high-performance digital signal processing (DSP), the design methodology
gap between software DSP implementation in DSP processors and hardware
DSP implementation in FPGA or ASIC technology has grown increasingly
apparent. FPGAs (particularly those with hardware DSP features) offer
compelling advantages in cost, performance, and power consumption for
super-power number crunching. Getting your ideas into one, however, is
still many times more difficult than programming a software processor
to do the same thing.
Implementing your favorite algorithm in a DSP processor
usually requires a few lines of C code, a compiler, and a few days
of a competent software specialist’s time. Creating a hardware
implementation, from the perspective of the DSP designer at least,
is a mysterious black art in the domain of the double Es down the hall.
It requires weeks to months of time, a knowledge of hardware architectures
and hardware description languages (HDLs), a confusing suite of design
tools, and often involves a great deal of lost sleep.
Luckily, the design tool community has noticed
this problem and continues to work furiously to upgrade and enhance
the software and design processes that enable this high-value implementation
path. As with any relatively new design science, there is no established “best” way
to get from DSP algorithms into hardware. There are a diverse set of
approaches, each with its own strengths and weaknesses, and a general
trend toward higher productivity, easier learning curves, and more
efficient results.
Today’s design approaches generally emanate from
either an IP-based source or from an algorithmic source. A couple of
the more sophisticated solutions leverage benefits of both. The number
and variety of companies and products vying for supremacy in this hotly-contested
and potentially lucrative segment grows almost monthly. Just about everyone
involved in programmable logic has acknowledged that, along with embedded
processing applications, DSP represents one of the largest growth potential
areas for FPGA over the next several years. [more]
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Accelerating
Embedded DSP Design for FPGAs.
Announcing AccelChip DSP Synthesis 2004.6. Now with improved MATLAB
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Download
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|
Hire the best FPGA talent in the industry with
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|
FPGA Journal has teamed
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More
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The Xilinx Virtex-4 LX25 Evaluation
Kit from Avnet
Electronics Marketing helps design engineers get started
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QuickLogic and Renesas present a free web
seminar on Thursday, December 9th at 10:00 a.m. (PST)
Adding Wi-Fi or IEEE 802.11a/b/g functionality
to embedded systems is gaining in popularity. Quite
often however, Wi-Fi modules do not have the same native
interface as the embedded processors used in these
systems. We will specifically look at how this problem
can be solved for portable applications where engineers
constantly struggle with very tight power requirements
and limited board space.
Click
here to register.
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