| FROM
THE EDITOR
This week we have three new articles on high-volume cost reduction.
When you take your product to volume, you need to engineer beyond
the logic. You have to take economics into account and plan a solution
that will get you to market the fastest with the lowest effective
unit cost.
Our feature article “Cost
Reduction Quagmire” describes
many of the available cost reduction options and gives some guidelines
as to when you might want to use each. Next, we have a pair of
articles from Xilinx and Altera each making the case for their
approach to cost reduction directly from an FPGA-based design.
In coming weeks, we also plan to run contributed
articles telling the structured ASIC side of the story, which
is very compelling if your design won’t fit on a single
FPGA or demands higher performance and less power consumption
than programmable logic will allow. Boosted by recent design
wins, structured ASIC is now starting to come into its own as
a fast-to-market alternative to both cell-based ASIC and FPGA,
fitting nicely into the gargantuan gap between those two popular
technologies.
Thanks
for reading! If
there's anything we can do to make our publications more useful
to you, please let us know at: comments@fpgajournal.com
Kevin Morris – Editor
FPGA and Programmable Logic Journal
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Cost-Reduction
Quagmire
Structured ASIC and Other Options
Your design is working perfectly – on your
development board.
Unfortunately, your company is probably not planning
to ship FPGA development boards as part of their product. You'll have
to come up with something a little more practical and cost effective
if you're going to win "employee
of the decade" when your skunk-works design ships one million units.
There is general consensus, even among ASIC suppliers, that FPGAs are
the highest productivity platform for getting your design debugged and
running in actual hardware. If you have an idea, and you want a hardware
implementation of that idea as quickly as possible, nothing will get
you there quicker (or cheaper) than downloading a set of FPGA tools,
buying a development board with the required device, I/O, and peripherals,
finding a reference design that looks something like what you're trying
to build, hooking up some good-quality IP cores, and writing VHDL or
Verilog for any missing pieces. I have confirmed this repeatedly, with
design team after design team, in almost every conceivable application
area.
Recently (at Denali's MemCon, actually), I listened
to a panel session debating the relative merits of FPGAs and structured
ASIC. The panel featured representatives from major FPGA and structured
ASIC companies, and it took almost no time for the panel to agree on
what we already stated. Everyone should start his or her system design
with FPGAs. The interesting part of the debate was what followed, and
the answers were (as in any public discussion between parties with
a stake on opposite sides of the issue) quite obscured by FUD-injected
marketing rhetoric. (For those of you who haven't taken a course in
confrontational marketing recently, "FUD" stands for fear, uncertainty, and doubt – generally
directed toward whatever your competitor is offering.) [more]
Customer-Specific
FPGAs: Low Cost Solution for Volume Production
by Gokul Krishnan and Balaji Thirumalai,
Xilinx, Inc.
The risks associated with ASIC solutions increase in
magnitude with the move to smaller process geometries. This coupled with
the increase in design complexity is compelling companies to look for
viable technology options that offer low unit and total costs, high-level
of system integration, wide selection of IP, design flexibility with
faster time to market, and no/minimal incremental design or design tool
investment. Such alternatives must also avoid the pitfalls of ASICs that
include high NRE and re-spin expenses, slow turn around times, and complexity
of the design environment and ecosystem, and hidden costs of conversion,
verification and development.
This article will compare two such alternatives -- (customer-specific)
FPGAs and Structured ASICs. Structured ASIC product offerings tend to
be similar to FPGAs in that they have pre-defined combinations of gates,
memory and I/Os. However, their architectures tend to trade off flexibility
in favor of reduced area in order to achieve their cost targets. Yet,
in reality the vast majority of designs that are expected to go into
volume production are initially prototyped in an FPGA. Ultimately, the
decision becomes a risk-reward evaluation of the migration path from
an FPGA to Structured ASIC conversion or to the new class of customer-specific
FPGAs that offer a conversion-free path to high volume production devices
priced below Structured ASICs. [more]
Living in the Product Development "Valley
of Death"
by Jack Ogawa, Senior Director, ABG Solutions Marketing, Altera
Corporation
Fiscal Focus
The recent downturn in the semiconductor industry, unprecedented in
its magnitude and duration, has forced application specific standard
product (ASSP) vendors to improve the fiscal efficiency of their product
development processes and capabilities, with the intent of maximizing
return-on-investment (ROI). Improving development capability and efficiency
will lower non-recurring costs, and will also lower the cost of goods
sold (COGS), resulting in improved profitability. Successful ASSP companies
understand the fiscal benefit of strong design capability and actively
seek opportunities for improvement.
Unfortunately, Moore’s Law works against
development efficiency. Increasing device complexity enabled by increasing
transistor density is driving development costs up faster than efficiency
tools such as EDA software can bring them down. As a result, fewer
ASSP product proposals can successfully demonstrate a reasonable ROI
and therefore are not funded. [more]
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