| FROM
THE EDITOR
This week we sneak a peek into the secret labs of EDA and FPGA
vendors to examine the back room black art of benchmarking. In
these places, giant racks of high-speed servers grind away tirelessly
trying to figure out if a new synthesis algorithm improves timing,
or if a new FPGA architecture’s routability is adequate.
The companies that provide FPGA tools and technology invest considerable
expertise, time, and money measuring their progress and trying
to size up their competition.
Next week, we’ll be taking an in-depth look
at the options for taking your design into large-volume production
including structured ASIC, low-cost FPGA, and a number of innovative
alternative solutions.
Thanks
for reading! If
there's anything we can do to make our publications more useful
to you, please let us know at: comments@fpgajournal.com
Kevin Morris – Editor
FPGA and Programmable Logic Journal
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Benchmarking
Battlefield
Measuring the Metrics of FPGA Technology
In our previous article “Terminology
Tango 101” we
poked fun at the myriad metrics given by programmable logic companies
in their publications and data sheets. While it’s fun to make fun
of the confusion induced by this dizzying data, it is also interesting
and useful to dig past the difficulties of agreeing on units and dimensions
and to take a look at the actual processes that are used to test our
tools and evaluate our architectures. While there is a good deal of obfuscation
built into the numbers that are presented to the public, the companies
that publish them do make a significant effort to measure accurately
and inform realistically. The problem is that constructing and conducting
an accurate and reasonable test of FPGA tool and architecture performance
is incredibly complex.
Domain Specific Dilemma
First, we need to understand that the range of
applications being targeted to programmable logic is growing broader
every day. In the past, it was interesting and relevant to publish
an estimated gate count and a rough idea of maximum operating frequency
as a means of informing the design community of the capabilities of
a particular FPGA architecture. Today, however, with FPGAs containing
a wealth of embedded hard IP and being used for everything from digital
signal processing, to embedded and reconfigurable computing, to high-speed
serial I/O, it is virtually impossible to measure and report on what’s
relevant to every design team considering a particular tool or technology
for their project.
FPGA companies have mostly abandoned counting equivalent
ASIC gates or “system gates” in favor of reporting the number
of logic cells or look up tables (LUTs) contained in a particular architecture.
Now, however, with devices containing vast numbers of embedded multipliers,
huge amounts of block and distributed RAM, high-performance RISC processors,
and a host of complex I/O hardware, the LUT count is only a small part
of the story. Likewise, measuring the clock speed of the programmable
LUT fabric misses much of the relevant performance potential of a device
in a real application. Factors such as the serial I/O bandwidth, the
equivalent DSP performance, and the processing power are probably even
more meaningful today than old-school FPGA metrics. [more]
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