I once commented to a colleague that every EDA presentation ever given follows a basic script:

Presenter: Moore’s Law!
Audience: Oh no! What shall we do?
Presenter: Don’t worry. We have a new EDA tool that’ll save you.
Audience: What a relief.

If that is true, then every semiconductor presentation might have an analogous script:

Presenter: Moore’s Law!
Audience: Oh boy! What do we get?
Presenter: Bigger, faster, cheaper.
Audience: Yaaay!

This week, we’re celebrating the “cheaper” part of that script, applied to programmable logic. We’ve covered several announcements over the past year that, taken together, have significantly changed the programmable logicscape. Beginning with Altera hitting the $12 USD for 1 million gates watermark with their original Cyclone series, the capability and diversity of low-cost FPGA lines have headed steadily up and to the right.

While the “to the right” part of that graph isn’t particularly interesting (hey, time marches on…) the “up” part has some exciting news for patrons of programmables in the high-volume, low-cost arena. Contending for your monetary mindshare are three FPGA families and, um, another FPGA family pretending to be a CPLD.

Leading our list is the first-to-market 90nm low-cost FPGA family from Xilinx, Spartan 3. Lest we be confused, Spartan 3 is the aptly named Xilinx family that followed Spartan and Spartan 2. Since we’ve received over 50 reader e-mails on this question, maybe we should re-clarify the Xilinx lines. The latest two Xilinx families, both based on 90nm design rules, are Spartan 3 (low cost) and Virtex 4 (high performance/density). The previous generation (130nm design rules) included Spartan 2 and Virtex II (and Virtex II-Pro). Virtex 3 does not exist. It apparently fell into a Virtex vortex and those who have gone in search of it have never returned. Xilinx claims that Virtex II Pro is actually the missing Virtex 3, but DNA tests have yet to be performed.

Now back to our “low-cost” discussion. Spartan 3, which Xilinx recently announced has passed the “one million units shipped” milestone, is available in densities ranging from 50,000 to 5 million system gates. In more understandable terms, the family ranges from 1,728 to 74,880 logic cells, with proportional servings of other nice features such as block RAM (72K-1872K bits), I/O (124-784 single-ended), and 18X18 multiplier blocks for DSP use (4-104). Xilinx claims a 326MHz system clock rate for the family. [more]