It never makes the marketing materials. You don’t see an ad saying “New Super RISC Core is Stickier than Ever!” There is generally no mention of the word “sticky” in datasheets, white papers, or application notes. Suppliers of Intellectual Property (IP) cores (the overly-broad label that’s commonly applied to pre-engineered components that you can drop into your design, saving time, errors, and design effort) tout the speed, configurability, reliability, density, and power efficiency of their offerings, but never the “stickiness.” Unless you listen carefully to conversations in hallways, meeting rooms, and strategy planning sessions at EDA, FPGA, and even IP vendors, you might never become acquainted with the concept of “stickiness” at all.

What, then, is “sticky IP”? Simply put, “sticky IP” refers to the type of IP cores that, when designed into your circuit, make it difficult for you to transition to a different silicon, software, or IP vendor. This marketing strategy is not new. It is at least as old as the concept of selling razors at a loss so people will be locked into buying your blades instead of your competitor’s, or almost giving away the camera so people will have to buy your film. In many circumstances, the consumer benefits along with the supplier. In the case of IP, the cost of development is relatively high, and the audience is small. Amortizing those development costs over such a small audience can be a significant challenge for suppliers trying to make a business just from the IP itself. Consolidating the sales and distribution of IP with other mandatory components (silicon, software tools, etc) reduces the sales, marketing, and operations overhead in the process and generally gives a higher value to the consumer. [more]

Accelerating ASIC Verification with FPGA Verification Components
by Rohit Dubey - eInfochips

With the ever-increasing size and density of ASIC, conventional simulation-based verification has become a bottleneck in the project development cycle. In conventional verification, the simulation time steadily increases as the design matures in terms of bug count.

The verification community has resorted to different methodologies to overcome this. They are trying to reduce the development time by introducing Verification Components and Hardware Verification Languages (HVL). These help in terms of reusability but do not attend to the issue of simulation time. On one side, where the HVL provides better features such as higher level of abstraction and better randomization, the normal simulation time increases significantly. The additional random generation logic and higher level of abstraction, along with PLI calls, reduces the simulation speed. As shown in Figure 1, as the design matures, it becomes tougher to find bugs, resulting in longer simulation time. Now randomization has increased to find more bugs using HVL, which increases the simulation time and overall development time. [more]