The news has been slowly leaked like the plot to an upcoming summer blockbuster movie. First, there is “the teaser.” In movies, this is a 30 second preview that gives only the most basic hint of the film. In our case, this was Xilinx’s ASMBL architecture announcement that came out in December 2003. Xilinx outlined the next-generation floorplan, explaining that it would be rich in hard IP, grouped into what the company called “columns”. They also revealed that the new family would enable a number of product variants focused on different application domains. Each variant would have a different mix of hard IP optimized for a particular type of application.

As the summer approaches, the audience is treated to “the trailer,” which is a more involved preview, typically up to a couple minutes in length, showing many of the plot elements of the final film. Virtex 4’s “trailer” came out in June, announcing details of the family and putting much of the speculation generated by the architecture announcement to rest. No, there would not be a substantial change to the LUT-based FPGA fabric architecture. No, there would not be hundreds of variations of Virtex 4 devices aimed like ASSPs at particular target applications. There would be three flavors initially. One optimized for DSP, one optimized for high-speed serial I/O and embedded processing, and one more general-purpose “classic” FPGA.

In movies, the next stage is usually a “test screening.” This is a limited showing of the final film to a selected audience to gauge reaction and to solidify plans for the eventual production launch. Virtex 4 has now completed its test screening, and Xilinx is evidently pleased with the results. Their early access customers have completed their first designs, and they’re ready to move on to the next level of deployment. [more]