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THE EDITOR
This week we take a look at advances in the integration of tool flows between FPGA and board design environments. Mentor Graphics' new I/O Designer keeps pin assignments synchronized between the two design domains and smoothes the process of iterating and converging on a workable design.
We also have an article from Anadigm’s Ian Macbeth on new field programmable analog arrays. Sometimes, digital just won’t do the job, and FPAAs may be the solution. Ian discusses the architecture and tool basics of FPAA design.
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Kevin Morris – Editor
FPGA and Programmable Logic Journal
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LATEST NEWS
Tuesday, July 20, 2004
Actel FPGAs Play Critical Role in Uncovering Origins of the Solar System
National Semiconductor Introduces Power Management Solutions for Xilinx FPGAs
Altera Begins Shipping MAX II Devices, Industry's Lowest-Cost CPLDs
SBS Technologies Dual FPGA Computing Platform Lowers Cost for Military and Commercial Applications
Monday, July 19, 2004
Atmel Offers World's First Commercially Available 32-Mbit FPGA Configuration Memories
Altera Net Seminar: Save Time and Money by Using Programmable Logic as an ASIC Design Alternative
Xilinx Ships More Than 1.5 Million Pb-free and RoHS-Compliant Units
Xilinx Delivers the Industry's Fastest High-Speed Serial Transceivers
Mentor Graphics Introduces the Industry's First Concurrent Chip-to-Board Solution for FPGA and PCB Design
Lattice Announces ispLEVER 4.1 Design Environment for New LatticeECP-DSP and LatticeEC FPGAs
QuickLogic Adds to PCI Embedded Standard Product Family; QuickPCI Combines a PCI Controller with Programmable Logic for a Complete and Customizable PCI Interface
Wednesday, July 14, 2004
Mercury Computer Systems Selected by Lockheed Martin for Joint Common Missile Program
Tuesday, July 13, 2004
Oak Ridge National Laboratory Selects Spectrum Signal Processing's SDR-3000 Platform for Multiple Research Programs, Including RF Identification Application Development
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Board Room
Mentor Tackles FPGA on PCB
The contest begins. On the left side of the hall (the “blue” corner), the FPGA design team iterates through the design loop with their high-performance design tools, looking for the optimal placement to reach timing closure. As paths are probed and placements are optimized, it becomes apparent that the problem is the pin assignment. After swapping a few I/O constraints around and re-running place-and-route, the design clears timing analysis with flying colors. Positive slack for all!
On the right side of the hall (the “red” corner), this is all bad news. The board design team had a pretty solid layout done based on the old pin assignment. When the new constraints fly in the door scrawled on a paper airplane from across the hall, they spend hours re-creating the design only to find out that their carefully matched bus traces are now scattered to the four winds. The board design team tries to retaliate with pin-assignment changes of their own, but the FPGA team has already left for vacation. The red team is left to trombone their way to tuned trace lengths, wasting precious board space and increasing design cost.
As FPGA tools have evolved over the past few years, the basic task of FPGA design has gotten easier. LUT-for-LUT, it is now faster than ever to get a working FPGA design loaded into your device. FPGA synthesis and place-and-route tools have continued to improve in speed, stability, and quality of results. According to FPGA Journal’s 2003 FPGA market study, these “core” steps in the design process new occupy less than 1/3 of the overall FPGA design cycle. [more]
Programmable Analog
by Ian Macbeth, Anadigm, Ltd.
System platform-based design(1) is one of a number of high-level initiatives to tackle the spiraling problems of design complexity, hardware/software integrity and cost. The approach aims to stratify a system design problem into bite-size layers. It also aims to deliver higher, unified abstractions from existing digital EDA flows. Each platform must:
-map an instance in an (upper) application space to another in a (lower) architecture space
-communicate constraints between these spaces in forms suitable to each
-package the application solution in a form suitable for deployment and integration by the platform above it
This demands massive standardization of methodology. Such discussions have been largely irrelevant to analog design which is very much a custom process, independent of the rest of the system design (whether it be integrated or discrete). [more]
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