a techfocus media publication :: April 20, 2004 :: volume III, no. 3


FROM THE EDITOR

It’s time to slip on our space suits as we go for a ride in the upper atmosphere where sinister Galactic Cosmic Rays are causing all sorts of trouble for our hardware-designing heroes, even way down here on the ground. This week we talk about neutron-induced single-event upsets (SEUs) and what you need to know about them when designing systems with FPGAs. A new report released this week continues this long-standing controversy.

Next week, we look at signal integrity, and how it’s becoming an increasingly big headache for FPGA designers, particularly those of us taking advantage of gigabit I/O capabilities of the latest devices.

Thanks for reading!

If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal

LATEST NEWS

Tuesday, April 20, 2004

Altera Delivers Two Millionth Cyclone Device to Matsushita Electric

QuickLogic Introduces Its Low-Power PCI Embedded Standard Product Family

Hier Design Adds Movaz Networks to Customer List; Movaz Networks Will Implement PlanAhead Into Design Flow

Xilinx Achieves PLD Industry's First TL 9000 Registration, Enables Higher Quality FPGA-Based Telecom Systems

Monday, April 19, 2004

Industry Report Sheds Light on FPGA Reliability

QuickLogic Partners with Aldec to Provide Advanced Simulation Capability

Aldec Releases Riviera 2004.04 With Extended Verilog 2001 Support and a New Assertions Manager

Friday, April 16, 2004

Mentor Graphics Appoints New General Manager for Ready-to-Use PCB Design Products

More Than 35 Companies and Universities Present in the 1st International System-on-Chip Conference and Exhibition Newport Beach, California

Exhibition for Leading-Edge ASIC/SoC Technologies and Tools at the 1st International System-on-Chip Conference April 19th, Radisson Hotel Newport Beach

Thursday, April 15, 2004

Actel to Present Three Papers at Mentor Graphics' user2user Conference 2004

Wednesday, April 14, 2004

Modulus Video Licenses H.264 Technology From LSI Logic to Develop Next Generation Broadcast Video Compression Systems

Aspex Secures US$10 Million in Second Round Equity Funding, Changes Name to Aspex Semiconductor

ANNOUNCEMENTS

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UltraController™ Workshop
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Upset with Neutrons
Will SEUs hit the FPGA in your SUV?

The cosmos are conspiring against your FPGA. From millions of light years away, they are seeking out our semiconductors, targeting our technology with high-energy particles that can silently flip our flip-flops, reconfigure our routing, and tamper with our look-up tables. Galactic Cosmic Rays (GCRs) are the highest energy particle radiation to reach earth. The majority are shielded from the earth by the earth’s magnetic field. However, some particles still penetrate this protection. Upon entering the atmosphere, they collide with atmospheric gases, producing a wide variety of subatomic particles, including a significant quantity of high-energy neutrons. The greatest density of these neutrons occurs at an altitude of about 60,000 feet. Below that level, they are gradually attenuated by the atmosphere so there is a much lower density at the earth’s surface. Even at ground level, however, neutrons sometimes strike semiconductor devices. When one of these hits a configuration bit of your SRAM FPGA, it can change the routing or alter the behavior of a look-up table, producing incorrect logic until the device is reconfigured.

After reading the new 79-page report entitled "Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA Instances" recently published by iRoC technologies, you may be tempted to run to the kitchen to fashion yourself a protective tinfoil hat (as well as a tiny one for your smart-phone.) If you consult your copy of “The WORST-CASE SCENARIO Survival Handbook” the table of contents offers little hope: “How to escape from quicksand,” “How to fend off a shark,” “How to wrestle free from an alligator…” Unfortunately there’s no chapter on “How to avoid neutron-induced single-event-upsets in your SRAM FPGA.”

Before you bolt down the door to your bunker, let’s check in with a recognized authority on things that happen to electronics in space. Ken LaBel from NASA Goddard Space Flight Center makes a career of studying radiation effects on semiconductor devices. “In space,” LaBel comments, “we worry a lot about this stuff. The most difficult to deal with are these single particle effects such as single event upsets (SEUs).” A single particle can strike a memory element, causing it to change state randomly. In radiation-intense environments like the upper atmosphere and in space, these events are common, and systems must be designed to compensate for them. On the ground, LaBel says, the problem is far less troublesome. The relatively small number of neutrons reaching devices at sea level makes the likelihood of an SEU-induced error much lower.

For the record, however, there are numerous SRAM FPGAs operating successfully, even in the harshest space environments. “The Mars Rovers relied on Xilinx devices to control the descent, including rockets and parachutes,” says Xilinx’s Peter Alfke, “and they also have one Virtex device in each wheel, where they (along with other devices) measure torque that relates to the surface condition.” Systems such as these are typically designed using techniques such as configuration read-back and refresh, and triple-module redundancy to take SEUs into account along with the myriad other difficulties faced by designers developing electronics to work in space. Designers of terrestrial applications may not want to resort to these techniques, but should exercise the same engineering rigor depending on the demands of their application.

While there are a number of radiation-induced hazards that affect all semiconductors, SEUs are in a category known as “soft errors,” meaning they don’t do permanent damage to the device; they merely effect a temporary change of state. Other types of errors include hard errors in memory cells such as gate or dielectric rupture; or latchup which can damage or destroy the device. In an FPGA, not every SEU generates a logic error, since any given design uses only a small number of the configuration cells in a device. [more]


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