Aurora Lightweight Gigabit Serial Protocol
by Abhijit Athavale, Xilinx, Inc.

The System Interconnect Challenge. As CPU speeds approach the multi-gigahertz range, system designers increasingly focus on system interconnect as the primary bottleneck at all levels, viz: chip-to-chip, board-to-board, backplane, and box-to-box. Most of the system interconnect used today uses parallel I/O technology with either source-synchronous clocking or system-synchronous clocking. The venerable PCI bus is the prime example of a system-synchronous interface that has served the industry well over the past decade. PCI uses a central arbiter that allows sharing of a common bus between several clients. This has obvious limitations since the bus bandwidth is not infinite – this in turn limits the capabilities of the clients. Additionally, this technology does not scale well when translated to backplane or box-to-box interconnects. Source-synchronous technologies using LVDS I/O were the next obvious choice for designers as they are point-to-point interconnects that do not have a central arbitration scheme bottleneck. However, these schemes suffer from the same problem that PCI based schemes did when scaling the technology across backplanes or box-to-box interconnects. Not only do designers have to run tens or even hundreds of traces in some cases over many inches of FR4, they also have to be mindful of the lane-to-lane data and the clock-to-data skew. A bit arriving too early or too late can cause serious link integrity problems. [more]

SoC Prototyping Requirements
by Raj Mathur, Aptix Corporation

For an SoC chip, the validation of hardware, software, and firmware on a common platform can be accomplished using FPGA-based prototypes. FPGA prototypes make it possible for SoC designs to be delivered on time, on budget, and on market target. For successful design testing with prototypes, tools need to provide automation while maintaining flexibility. This article focuses on what's required in an RTL–to–PCB mapping and debugging flow that targets multiple state-of-the-art FPGAs. Requirements such as hardware/software testing, design checking, partitioning, co-emulation, debug, FPGA synthesis and place-and-route, IP encryption, and hardware self-test will be discussed.

So, let’s begin with a quick review of what exactly distinguishes an SoC design from a traditional ASIC. From the picture of an SoC [Figure 1], it looks much like any other IC. Functionally, however, it includes components like CPUs, DSPs, and memory that have traditionally been in separate chips. In SoC designs, external IP plays a much larger role. The designs are simply too big and complex to be developed from scratch within a single organization. Where custom logic is used, there is tremendous emphasis on re-use of existing design work, rather than re-inventing the wheel for each design. Another difference with SoCs is the emphasis on being able to roll out derivative products quickly. Companies want to capitalize on market successes by making small changes to existing designs to target new market niches. The biggest single difference between SoCs and traditional ASICs, however, is the importance of software. Software has become the key differentiator among products and often requires the lion’s share of development time. [more]