Mr. Moore's Wild Ride - 90nm FPGAs go mainstream

Designing with FPGAs offers you protection. It offers protection from the risk of ASIC re-spins and NRE, protection from design rule worries, protection from test generation, protection from high-cost design tools… The FPGA vendor did all the work, took all the risks, and made all the mistakes for you, so you could design in peace and harmony, unthreatened by the demons and dragons of IC design and process technology. From the “safe” side of that protective wall, however, it’s sometimes difficult to discern whether the barrier is getting gradually thinner.

As each process generation has brought its new challenges, programmable logic vendors have responded with new, innovative architectures, more capable tools, and improved methodologies. The recent announcement by both Altera and Xilinx of 90nm-based devices rings the opening bell on the next round of this game. 90nm is clearly the most challenging geometry jump of the decade, and FPGA vendors continue to struggle to bring to designers the benefits of the technology while preserving the wall of safety that makes FPGA the world’s most popular technology for implementation of customized logic.

The 90nm challenge is a multi-dimensional contest. FPGA vendors are seeking to expand their technologies to broader markets, diversifying their way to safety from the vagaries of the volatile communications market whose roller-coaster ride rocketed them to prominence in the late 1990s only to plummet them into the grips of the recession of the early new millennium. They are also working to differentiate their product offerings and add value as the pending expiration of patent portfolios threatens to homogenize and commoditize the market. Crossing these strategic agendas are the technical challenges of the process geometry itself: increased power dissipation due to leakage current, greater noise susceptibility, compatibility of the lower-voltage process with legacy technologies, and the usual yield challenge in bringing up a new generation. At the same time, most fabs are also midway through the transition from 200mm to 300mm wafers.

At the nexus of this melee are the marketing machines of the vendors themselves, each working to position their company as technology leader and supplier of choice for a new wave of inductees into the programmable logic club. It is here that the drama unfolds. Xilinx made the early push into 90nm, fueled at the time by UMC’s apparent lead over TSMC in the new process. Having experienced a greater-than-anticipated struggle with their 130nm lines, they were emboldened to jump ahead into the 90nm market.

In a sharp departure from convention, expectation, and the rest of the pack, Xilinx decided to bring their low-cost Spartan line to production first rather than their high-end Virtex line. Analysis of the factors involved reveals this to be a well-conceived, bold, and strategic move. First, the challenge of yield could be partially overcome by the relatively smaller die size of the low-cost line. Second, the square millimeters shaved off of each die translated into square watts of heat that didn’t have to be dissipated in fighting the power glut induced by the step increase in leakage current at the 90nm node. Third, in the effort to diversify out of the high-cost telecommunications market into more cost-sensitive application areas, a highly competitive low-price product would be a strategic advantage, particularly to counter the highly successful price/performance point of arch-rival Altera’s successful Cyclone line. [more]