Stratix II - Altera unveils new 90nm architecture

Sides have been chosen. The gauntlet has been thrown down. The battle lines for the next generation of programmable logic have been drawn, and the games may now begin. Altera today announced its first 90nm FPGA architecture, and their strategy and offering contrasts sharply with that of arch-rival Xilinx. While it is far too early to call a winner in this contest, it is already crystal clear that the competition will be interesting, exciting and nothing but good news for FPGA designers.

Following the success of their highly regarded Stratix family, Altera today announced Stratix II. While movie-goers have long been trained that the sequel never lives up to the original, Stratix II represents a significant step forward from its namesake architecture.

New FPGA Fabric Architecture

Yes, Stratix II is built on 90nm technology, but that’s only the beginning. Belying the “II” moniker, this is a completely overhauled architecture that happens to also leverage the next process node. First and foremost on the list of changes is the radical (to those who follow FPGA architecture) departure from the traditional 4-input logic cell. 4-input look-up tables (LUTs) have been the stalwart atomic structure in FPGA for a number of years. Numerous analyses, experiments, and academic papers have shown that, on average, a 4-input structure is the most efficient fixed-size basic cell for generic implementation of most types of logic design.

Altera chose to break with that tradition; they have developed a novel variable-width cell called an “Adaptive Logic Module (ALM)”. An ALM looks something like a 7-input LUT (or 8 depending on how you count) that can be flexibly re-partitioned into a number of configurations such as 5 inputs + 3 inputs or 4 inputs + 4 inputs. With input sharing, larger combinations can be created, such as 5 + 5 or even 6 + 6. According to Altera, this architecture allows the best of both worlds – the efficiency of narrow logic elements with the performance of wide ones. With a 4-input LUT, for example, a 5-input function could require 2 levels of logic and up to 3 LUTs to implement. With the ALM, a 5-input function can be implemented in a single ALM with one level of logic and still leave room for an optional 3-input function (which might have required yet another 4-input LUT in the original case). This means substantially fewer gates are needed to implement the same logic, and often fewer levels of logic between registers. The net effect should be less area, higher performance, and fewer routing resources consumed. [more]