FPGA Journal Update

On-Chip Debugging
Built-in logic analyzers on your FPGA

Your FPGA is a walled city. Hidden inside this almost impenetrable silicon fortress is a vast network of internal signals connecting every component of your design, visible only through the window of a few tiny I/O pads. Through some ironic conspiracy of probability, statistics, and Murphy’s Law, the one with the error (the signal connected to the bad logic that’s holding up your design project right now) is almost never directly reachable through one of those pads. If only you could see past these I/Os, you could find and fix the problem. You need a Trojan horse, something you can smuggle into the core of the device past the I/O ring, that can spy on those internal signals and send back coded secret messages to let you know what’s going wrong.

According to our FPGA project survey, over 40% of FPGA designs are I/O limited. That means the designer couldn’t use a smaller or cheaper part because there weren’t enough pins and I/Os to get the required data on and off the chip. Even with skyrocketing pin-counts on the latest packages, pins are still at a premium and relative to the number of internal signals. Visibility into the workings of your design for debug is a problem now that will only get worse as devices grow.

With the advent of system-on-chip FPGAs (FPSOCs), the problem gets exponentially worse. First, the hardware component of most design is constructed from many large blocks of IP. Usually, these blocks were not written by the design team themselves. If the design is commercial IP, it is often also encrypted in a way that restricts visibility for debugging. Second, FPSOC designs are an order of magnitude more complex than typical hardware-only designs, sometimes involving multiple processors running parallel embedded software modules communicating with dedicated hardware and shared memories over complex bus structures. [more]

Using FPGAs for DSP Image Processing
R. Williams, Hunt Engineering

The article looks at the commonly used image processing functions which it turns out break down into three distinct categories. Then it looks at using FPGAs to perform those functions and compares this approach with that of using a conventional processor. Finally it looks at how such an approach could be used in a real image processing system, considering the image acquisition through the processing to the presentation of results. It is then demonstrated that using a modular approach like that of HERON real time systems can quickly find you a solution for image processing with FPGAs. [more]

FPGAs Provide Acceleration for Software Algorithms
David Pellerin, Impulse Accelerated Technologies, Inc.
Milan Saini, Technical Marketing Manager, Xilinx, Inc.

The latest generation of FPGAs featuring embedded processors offer compelling platforms for hardware acceleration of computationally-intensive software algorithms. Design teams taking advantage of these platforms are finding FPGAs to be low-cost, low-risk platforms for application prototyping as well as for use in high-performance end-products.

Although hardware-savvy engineers have been quick to embrace embedded processor based FPGAs (or Platform FPGAs), the lack of adequate design methods and general unfamiliarity with hardware design concepts has limited traditional software and embedded application developers from seriously considering these platforms. FPGA-based applications have until recently been the exclusive domain of the hardware designer. [more]